The patch not only performs the conversion according to the JSON-schema
but also adds the missing parts:
- st,syscfg phandle
- st,stm32h743-rcc compatible
that were not documented but are still used by the drivers and must
therefore be included to ensure the patch submission tests do not fail.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
.../bindings/clock/st,stm32-rcc.txt | 138 -----------------
.../bindings/clock/st,stm32-rcc.yaml | 143 ++++++++++++++++++
2 files changed, 143 insertions(+), 138 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
deleted file mode 100644
index cfa04b614d8a..000000000000
--- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
+++ /dev/null
@@ -1,138 +0,0 @@
-STMicroelectronics STM32 Reset and Clock Controller
-===================================================
-
-The RCC IP is both a reset and a clock controller.
-
-Please refer to clock-bindings.txt for common clock controller binding usage.
-Please also refer to reset.txt for common reset controller binding usage.
-
-Required properties:
-- compatible: Should be:
- "st,stm32f42xx-rcc"
- "st,stm32f469-rcc"
- "st,stm32f746-rcc"
- "st,stm32f769-rcc"
-
-- reg: should be register base and length as documented in the
- datasheet
-- #reset-cells: 1, see below
-- #clock-cells: 2, device nodes should specify the clock in their "clocks"
- property, containing a phandle to the clock device node, an index selecting
- between gated clocks and other clocks and an index specifying the clock to
- use.
-- clocks: External oscillator clock phandle
- - high speed external clock signal (HSE)
- - external I2S clock (I2S_CKIN)
-
-Example:
-
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- clocks = <&clk_hse>, <&clk_i2s_ckin>;
- };
-
-Specifying gated clocks
-=======================
-
-The primary index must be set to 0.
-
-The secondary index is the bit number within the RCC register bank, starting
-from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
-
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
-
-To simplify the usage and to share bit definition with the reset and clock
-drivers of the RCC IP, macros are available to generate the index in
-human-readble format.
-
-For STM32F4 series, the macro are available here:
- - include/dt-bindings/mfd/stm32f4-rcc.h
-
-Example:
-
- /* Gated clock, AHB1 bit 0 (GPIOA) */
- ... {
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
- };
-
- /* Gated clock, AHB2 bit 4 (CRYP) */
- ... {
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
- };
-
-Specifying other clocks
-=======================
-
-The primary index must be set to 1.
-
-The secondary index is bound with the following magic numbers:
-
- 0 SYSTICK
- 1 FCLK
- 2 CLK_LSI (low-power clock source)
- 3 CLK_LSE (generated from a 32.768 kHz low-speed external
- crystal or ceramic resonator)
- 4 CLK_HSE_RTC (HSE division factor for RTC clock)
- 5 CLK_RTC (real-time clock)
- 6 PLL_VCO_I2S (vco frequency of I2S pll)
- 7 PLL_VCO_SAI (vco frequency of SAI pll)
- 8 CLK_LCD (LCD-TFT)
- 9 CLK_I2S (I2S clocks)
- 10 CLK_SAI1 (audio clocks)
- 11 CLK_SAI2
- 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
- 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
-
- 14 CLK_HSI (Internal ocscillator clock)
- 15 CLK_SYSCLK (System Clock)
- 16 CLK_HDMI_CEC (HDMI-CEC clock)
- 17 CLK_SPDIF (SPDIF-Rx clock)
- 18 CLK_USART1 (U(s)arts clocks)
- 19 CLK_USART2
- 20 CLK_USART3
- 21 CLK_UART4
- 22 CLK_UART5
- 23 CLK_USART6
- 24 CLK_UART7
- 25 CLK_UART8
- 26 CLK_I2C1 (I2S clocks)
- 27 CLK_I2C2
- 28 CLK_I2C3
- 29 CLK_I2C4
- 30 CLK_LPTIMER (LPTimer1 clock)
- 31 CLK_PLL_SRC
- 32 CLK_DFSDM1
- 33 CLK_ADFSDM1
- 34 CLK_F769_DSI
-)
-
-Example:
-
- /* Misc clock, FCLK */
- ... {
- clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
- };
-
-
-Specifying softreset control of devices
-=======================================
-
-Device nodes should specify the reset channel required in their "resets"
-property, containing a phandle to the reset device node and an index specifying
-which channel to use.
-The index is the bit number within the RCC registers bank, starting from RCC
-base address.
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register.
-For example, for CRC reset:
- crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
-
-example:
-
- timer2 {
- resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
- };
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
new file mode 100644
index 000000000000..ae9e5b26d876
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 Reset Clock Controller
+
+maintainers:
+ - Dario Binacchi <dario.binacchi@amarulasolutions.com>
+
+description: |
+ The RCC IP is both a reset and a clock controller.
+
+ This binding uses common clock and reset bindings
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ Documentation/devicetree/bindings/reset/reset.txt
+
+ Specifying softreset control of devices
+ =======================================
+
+ Device nodes should specify the reset channel required in their "resets"
+ property, containing a phandle to the reset device node and an index specifying
+ which channel to use.
+ The index is the bit number within the RCC registers bank, starting from RCC
+ base address.
+ It is calculated as: index = register_offset / 4 * 32 + bit_offset.
+ Where bit_offset is the bit offset within the register.
+
+ For example, for CRC reset:
+ crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
+
+ The list of valid indices is available in:
+ - include/dt-bindings/mfd/stm32f4-rcc.h for STM32F4 series
+ - include/dt-bindings/mfd/stm32f7-rcc.h for STM32F7 series
+ - include/dt-bindings/mfd/stm32h7-rcc.h for STM32H7 series
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: st,stm32f42xx-rcc
+ - const: st,stm32-rcc
+ - items:
+ - enum:
+ - st,stm32f469-rcc
+ - const: st,stm32f42xx-rcc
+ - const: st,stm32-rcc
+ - items:
+ - const: st,stm32f746-rcc
+ - const: st,stm32-rcc
+ - items:
+ - enum:
+ - st,stm32f769-rcc
+ - const: st,stm32f746-rcc
+ - const: st,stm32-rcc
+ - items:
+ - const: st,stm32h743-rcc
+ - const: st,stm32-rcc
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#clock-cells':
+ enum: [1, 2]
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ st,syscfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to system configuration controller. It can be used to control the
+ power domain circuitry.
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+ - '#clock-cells'
+ - clocks
+ - st,syscfg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32h743-rcc
+ then:
+ properties:
+ '#clock-cells':
+ const: 1
+ description: |
+ The clock index for the specified type.
+ else:
+ properties:
+ '#clock-cells':
+ const: 2
+ description: |
+ - The first cell is the clock type, possible values are 0 for
+ gated clocks and 1 otherwise.
+ - The second cell is the clock index for the specified type.
+
+additionalProperties: false
+
+examples:
+ # Reset and Clock Control Module node:
+ - |
+ rcc@40023800 {
+ #reset-cells = <1>;
+ #clock-cells = <2>;
+ compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ reg = <0x40023800 0x400>;
+ clocks = <&clk_hse>, <&clk_i2s_ckin>;
+ st,syscfg = <&pwrcfg>;
+ };
+
+ - |
+ rcc@40023800 {
+ #reset-cells = <1>;
+ #clock-cells = <2>;
+ compatible = "st,stm32f746-rcc", "st,stm32-rcc";
+ reg = <0x40023800 0x400>;
+ clocks = <&clk_hse>, <&clk_i2s_ckin>;
+ st,syscfg = <&pwrcfg>;
+ };
+
+ - |
+ rcc@58024400 {
+ compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+ reg = <0x58024400 0x400>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
+ st,syscfg = <&pwrcfg>;
+ };
+
+...
--
2.43.0On Sun, Jan 05, 2025 at 07:14:13PM +0100, Dario Binacchi wrote:
> diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
> new file mode 100644
> index 000000000000..ae9e5b26d876
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
> @@ -0,0 +1,143 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: STMicroelectronics STM32 Reset Clock Controller
> +
> +maintainers:
> + - Dario Binacchi <dario.binacchi@amarulasolutions.com>
> +
> +description: |
> + The RCC IP is both a reset and a clock controller.
> +
> + This binding uses common clock and reset bindings
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> + Documentation/devicetree/bindings/reset/reset.txt
Drop paragraph.
> +
> + Specifying softreset control of devices
> + =======================================
> +
> + Device nodes should specify the reset channel required in their "resets"
> + property, containing a phandle to the reset device node and an index specifying
> + which channel to use.
Drop paragraph and rephrase it that reset phandle argument is "... the bit
number within the RCC...."
> + The index is the bit number within the RCC registers bank, starting from RCC
> + base address.
> + It is calculated as: index = register_offset / 4 * 32 + bit_offset.
> + Where bit_offset is the bit offset within the register.
> +
> + For example, for CRC reset:
> + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
> +
> + The list of valid indices is available in:
> + - include/dt-bindings/mfd/stm32f4-rcc.h for STM32F4 series
> + - include/dt-bindings/mfd/stm32f7-rcc.h for STM32F7 series
> + - include/dt-bindings/mfd/stm32h7-rcc.h for STM32H7 series
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: st,stm32f42xx-rcc
> + - const: st,stm32-rcc
> + - items:
> + - enum:
> + - st,stm32f469-rcc
> + - const: st,stm32f42xx-rcc
> + - const: st,stm32-rcc
> + - items:
> + - const: st,stm32f746-rcc
> + - const: st,stm32-rcc
> + - items:
> + - enum:
> + - st,stm32f769-rcc
> + - const: st,stm32f746-rcc
> + - const: st,stm32-rcc
> + - items:
> + - const: st,stm32h743-rcc
> + - const: st,stm32-rcc
Old binding did not mention any fallbacks, so you need to explain this
in commit msg. You only said "st,stm32h743-rcc"
> +
> + reg:
> + maxItems: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + '#clock-cells':
> + enum: [1, 2]
> +
> + clocks:
> + minItems: 2
> + maxItems: 3
You need to list the items with description. Narrow the clock numbers
per varian in allOf:if:then and explain this in commit msg (old binding
did not say three clocks, so that's another change).
> +
> + st,syscfg:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to system configuration controller. It can be used to control the
> + power domain circuitry.
> +
> +required:
> + - compatible
> + - reg
> + - '#reset-cells'
> + - '#clock-cells'
> + - clocks
> + - st,syscfg
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: st,stm32h743-rcc
> + then:
> + properties:
> + '#clock-cells':
> + const: 1
> + description: |
> + The clock index for the specified type.
> + else:
> + properties:
> + '#clock-cells':
> + const: 2
> + description: |
> + - The first cell is the clock type, possible values are 0 for
> + gated clocks and 1 otherwise.
> + - The second cell is the clock index for the specified type.
> +
> +additionalProperties: false
> +
> +examples:
> + # Reset and Clock Control Module node:
> + - |
> + rcc@40023800 {
> + #reset-cells = <1>;
> + #clock-cells = <2>;
> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
> + reg = <0x40023800 0x400>;
compatible and reg are alwys the first.
> + clocks = <&clk_hse>, <&clk_i2s_ckin>;
> + st,syscfg = <&pwrcfg>;
Only one example.
> + };
> +
> + - |
> + rcc@40023800 {
> + #reset-cells = <1>;
> + #clock-cells = <2>;
> + compatible = "st,stm32f746-rcc", "st,stm32-rcc";
> + reg = <0x40023800 0x400>;
> + clocks = <&clk_hse>, <&clk_i2s_ckin>;
> + st,syscfg = <&pwrcfg>;
> + };
> +
> + - |
> + rcc@58024400 {
clock-controller@58024400
> + compatible = "st,stm32h743-rcc", "st,stm32-rcc";
> + reg = <0x58024400 0x400>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
> + st,syscfg = <&pwrcfg>;
So maybe just keep this example only.
> + };
> +
> +...
> --
> 2.43.0
>
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