From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Replace manual bit manipulation in `BUS_MSTOP` with `FIELD_PREP_CONST` and
`FIELD_GET` macros for better clarity and maintainability. Introduce
explicit masks (`BUS_MSTOP_IDX_MASK`, `BUS_MSTOP_BITS_MASK`) to improve
readability.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2->v3
- Dropped unnecessary parentheses
- Included RB tag from Geert
v1->v2
- None
---
drivers/clk/renesas/rzv2h-cpg.c | 4 ++--
drivers/clk/renesas/rzv2h-cpg.h | 5 ++++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 38edddfc42d9..23fb209d3232 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -582,8 +582,8 @@ static struct rzv2h_mstop
if (!mstop)
return NULL;
- mstop->idx = (mstop_data >> 16) & 0xffff;
- mstop->mask = mstop_data & 0xffff;
+ mstop->idx = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
+ mstop->mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
if (rzv2h_mod_clock_is_enabled(&clock->hw))
refcount_set(&mstop->ref_cnt, 1);
else
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 810275eba473..f918620c4650 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -46,7 +46,10 @@ struct ddiv {
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
-#define BUS_MSTOP(idx, mask) (((idx) & 0xffff) << 16 | (mask))
+#define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
+#define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
+#define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
+ FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
#define BUS_MSTOP_NONE GENMASK(31, 0)
/**
--
2.43.0On Thu, Jan 2, 2025 at 7:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Replace manual bit manipulation in `BUS_MSTOP` with `FIELD_PREP_CONST` and
> `FIELD_GET` macros for better clarity and maintainability. Introduce
> explicit masks (`BUS_MSTOP_IDX_MASK`, `BUS_MSTOP_BITS_MASK`) to improve
> readability.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v2->v3
> - Dropped unnecessary parentheses
> - Included RB tag from Geert
Thanks, will queue in renesas-clk for v6.14, with
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -8,6 +8,8 @@
#ifndef __RENESAS_RZV2H_CPG_H__
#define __RENESAS_RZV2H_CPG_H__
+#include <linux/bitfield.h>
+
/**
* struct ddiv - Structure for dynamic switching divider
*
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert, On Fri, Jan 3, 2025 at 5:08 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Thu, Jan 2, 2025 at 7:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Replace manual bit manipulation in `BUS_MSTOP` with `FIELD_PREP_CONST` and > > `FIELD_GET` macros for better clarity and maintainability. Introduce > > explicit masks (`BUS_MSTOP_IDX_MASK`, `BUS_MSTOP_BITS_MASK`) to improve > > readability. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- > > v2->v3 > > - Dropped unnecessary parentheses > > - Included RB tag from Geert > > Thanks, will queue in renesas-clk for v6.14, with > > --- a/drivers/clk/renesas/rzv2h-cpg.h > +++ b/drivers/clk/renesas/rzv2h-cpg.h > @@ -8,6 +8,8 @@ > #ifndef __RENESAS_RZV2H_CPG_H__ > #define __RENESAS_RZV2H_CPG_H__ > > +#include <linux/bitfield.h> > + > /** > * struct ddiv - Structure for dynamic switching divider > * > Thanks for taking care of this. Cheers, Prabhakar
Hi Prabhakar,
kernel test robot noticed the following build errors:
[auto build test ERROR on geert-renesas-drivers/renesas-clk]
[also build test ERROR on next-20241220]
[cannot apply to linus/master v6.13-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-rzv2h-Fix-use-after-free-in-MSTOP-refcount-handling/20250103-022238
base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link: https://lore.kernel.org/r/20250102181839.352599-4-prabhakar.mahadev-lad.rj%40bp.renesas.com
patch subject: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction
config: powerpc64-randconfig-001-20250103 (https://download.01.org/0day-ci/archive/20250103/202501031820.KwL9vVF2-lkp@intel.com/config)
compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250103/202501031820.KwL9vVF2-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501031820.KwL9vVF2-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/clk/renesas/r9a09g057-cpg.c:121:7: error: call to undeclared function 'FIELD_PREP_CONST'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
121 | BUS_MSTOP(5, BIT(10))),
| ^
drivers/clk/renesas/rzv2h-cpg.h:51:31: note: expanded from macro 'BUS_MSTOP'
51 | #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
| ^
>> drivers/clk/renesas/r9a09g057-cpg.c:120:2: error: initializer element is not a compile-time constant
120 | DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
121 | BUS_MSTOP(5, BIT(10))),
| ~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:148:2: note: expanded from macro 'DEF_MOD'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:17: note: expanded from macro 'DEF_MOD_BASE'
137 | .mstop_data = (_mstop), \
| ^~~~~~~~
2 errors generated.
vim +/FIELD_PREP_CONST +121 drivers/clk/renesas/r9a09g057-cpg.c
36932cbc3e6cc9 Lad Prabhakar 2024-07-29 116
36932cbc3e6cc9 Lad Prabhakar 2024-07-29 117 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
7bd4cb3d6b7c43 Biju Das 2024-12-13 118 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
7bd4cb3d6b7c43 Biju Das 2024-12-13 119 BUS_MSTOP_NONE),
7bd4cb3d6b7c43 Biju Das 2024-12-13 @120 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
7bd4cb3d6b7c43 Biju Das 2024-12-13 @121 BUS_MSTOP(5, BIT(10))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 122 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
7bd4cb3d6b7c43 Biju Das 2024-12-13 123 BUS_MSTOP(5, BIT(11))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 124 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
7bd4cb3d6b7c43 Biju Das 2024-12-13 125 BUS_MSTOP(2, BIT(13))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 126 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
7bd4cb3d6b7c43 Biju Das 2024-12-13 127 BUS_MSTOP(2, BIT(14))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 128 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
7bd4cb3d6b7c43 Biju Das 2024-12-13 129 BUS_MSTOP(11, BIT(13))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 130 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
7bd4cb3d6b7c43 Biju Das 2024-12-13 131 BUS_MSTOP(11, BIT(14))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 132 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
7bd4cb3d6b7c43 Biju Das 2024-12-13 133 BUS_MSTOP(11, BIT(15))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 134 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
7bd4cb3d6b7c43 Biju Das 2024-12-13 135 BUS_MSTOP(12, BIT(0))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 136 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
7bd4cb3d6b7c43 Biju Das 2024-12-13 137 BUS_MSTOP(3, BIT(10))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 138 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
7bd4cb3d6b7c43 Biju Das 2024-12-13 139 BUS_MSTOP(3, BIT(10))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 140 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
7bd4cb3d6b7c43 Biju Das 2024-12-13 141 BUS_MSTOP(1, BIT(0))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 142 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
7bd4cb3d6b7c43 Biju Das 2024-12-13 143 BUS_MSTOP(1, BIT(0))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 144 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
7bd4cb3d6b7c43 Biju Das 2024-12-13 145 BUS_MSTOP(5, BIT(12))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 146 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
7bd4cb3d6b7c43 Biju Das 2024-12-13 147 BUS_MSTOP(5, BIT(12))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 148 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
7bd4cb3d6b7c43 Biju Das 2024-12-13 149 BUS_MSTOP(5, BIT(13))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 150 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
7bd4cb3d6b7c43 Biju Das 2024-12-13 151 BUS_MSTOP(5, BIT(13))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 152 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
7bd4cb3d6b7c43 Biju Das 2024-12-13 153 BUS_MSTOP(3, BIT(14))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 154 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
7bd4cb3d6b7c43 Biju Das 2024-12-13 155 BUS_MSTOP(3, BIT(13))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 156 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
7bd4cb3d6b7c43 Biju Das 2024-12-13 157 BUS_MSTOP(1, BIT(1))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 158 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
7bd4cb3d6b7c43 Biju Das 2024-12-13 159 BUS_MSTOP(1, BIT(2))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 160 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
7bd4cb3d6b7c43 Biju Das 2024-12-13 161 BUS_MSTOP(1, BIT(3))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 162 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
7bd4cb3d6b7c43 Biju Das 2024-12-13 163 BUS_MSTOP(1, BIT(4))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 164 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
7bd4cb3d6b7c43 Biju Das 2024-12-13 165 BUS_MSTOP(1, BIT(5))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 166 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
7bd4cb3d6b7c43 Biju Das 2024-12-13 167 BUS_MSTOP(1, BIT(6))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 168 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
7bd4cb3d6b7c43 Biju Das 2024-12-13 169 BUS_MSTOP(1, BIT(7))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 170 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
7bd4cb3d6b7c43 Biju Das 2024-12-13 171 BUS_MSTOP(1, BIT(8))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 172 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
7bd4cb3d6b7c43 Biju Das 2024-12-13 173 BUS_MSTOP(8, BIT(2))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 174 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
7bd4cb3d6b7c43 Biju Das 2024-12-13 175 BUS_MSTOP(8, BIT(2))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 176 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
7bd4cb3d6b7c43 Biju Das 2024-12-13 177 BUS_MSTOP(8, BIT(2))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 178 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
7bd4cb3d6b7c43 Biju Das 2024-12-13 179 BUS_MSTOP(8, BIT(2))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 180 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
7bd4cb3d6b7c43 Biju Das 2024-12-13 181 BUS_MSTOP(8, BIT(3))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 182 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
7bd4cb3d6b7c43 Biju Das 2024-12-13 183 BUS_MSTOP(8, BIT(3))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 184 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
7bd4cb3d6b7c43 Biju Das 2024-12-13 185 BUS_MSTOP(8, BIT(3))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 186 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
7bd4cb3d6b7c43 Biju Das 2024-12-13 187 BUS_MSTOP(8, BIT(3))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 188 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
7bd4cb3d6b7c43 Biju Das 2024-12-13 189 BUS_MSTOP(8, BIT(4))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 190 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
7bd4cb3d6b7c43 Biju Das 2024-12-13 191 BUS_MSTOP(8, BIT(4))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 192 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
7bd4cb3d6b7c43 Biju Das 2024-12-13 193 BUS_MSTOP(8, BIT(4))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 194 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
7bd4cb3d6b7c43 Biju Das 2024-12-13 195 BUS_MSTOP(8, BIT(4))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 196 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
7bd4cb3d6b7c43 Biju Das 2024-12-13 197 BUS_MSTOP(9, BIT(4))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 198 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
7bd4cb3d6b7c43 Biju Das 2024-12-13 199 BUS_MSTOP(9, BIT(4))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 200 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
7bd4cb3d6b7c43 Biju Das 2024-12-13 201 BUS_MSTOP(9, BIT(4))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 202 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
7bd4cb3d6b7c43 Biju Das 2024-12-13 203 BUS_MSTOP(9, BIT(5))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 204 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
7bd4cb3d6b7c43 Biju Das 2024-12-13 205 BUS_MSTOP(9, BIT(5))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 206 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
7bd4cb3d6b7c43 Biju Das 2024-12-13 207 BUS_MSTOP(9, BIT(5))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 208 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
7bd4cb3d6b7c43 Biju Das 2024-12-13 209 BUS_MSTOP(9, BIT(6))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 210 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
7bd4cb3d6b7c43 Biju Das 2024-12-13 211 BUS_MSTOP(9, BIT(6))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 212 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
7bd4cb3d6b7c43 Biju Das 2024-12-13 213 BUS_MSTOP(9, BIT(6))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 214 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
7bd4cb3d6b7c43 Biju Das 2024-12-13 215 BUS_MSTOP(9, BIT(7))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 216 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
7bd4cb3d6b7c43 Biju Das 2024-12-13 217 BUS_MSTOP(9, BIT(7))),
7bd4cb3d6b7c43 Biju Das 2024-12-13 218 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
7bd4cb3d6b7c43 Biju Das 2024-12-13 219 BUS_MSTOP(9, BIT(7))),
36932cbc3e6cc9 Lad Prabhakar 2024-07-29 220 };
36932cbc3e6cc9 Lad Prabhakar 2024-07-29 221
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Prabhakar,
kernel test robot noticed the following build errors:
[auto build test ERROR on geert-renesas-drivers/renesas-clk]
[also build test ERROR on next-20241220]
[cannot apply to linus/master v6.13-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-rzv2h-Fix-use-after-free-in-MSTOP-refcount-handling/20250103-022238
base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link: https://lore.kernel.org/r/20250102181839.352599-4-prabhakar.mahadev-lad.rj%40bp.renesas.com
patch subject: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction
config: sparc-randconfig-002-20250103 (https://download.01.org/0day-ci/archive/20250103/202501030941.vDjx439p-lkp@intel.com/config)
compiler: sparc-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250103/202501030941.vDjx439p-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501030941.vDjx439p-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/clk/renesas/r9a09g057-cpg.c:15:
>> drivers/clk/renesas/rzv2h-cpg.h:51:34: error: implicit declaration of function 'FIELD_PREP_CONST' [-Wimplicit-function-declaration]
51 | #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
| ^~~~~~~~~~~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:32: note: in definition of macro 'DEF_MOD_BASE'
137 | .mstop_data = (_mstop), \
| ^~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:120:9: note: in expansion of macro 'DEF_MOD'
120 | DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
| ^~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:121:49: note: in expansion of macro 'BUS_MSTOP'
121 | BUS_MSTOP(5, BIT(10))),
| ^~~~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:120:9: note: in expansion of macro 'DEF_MOD'
120 | DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[1].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:120:9: note: in expansion of macro 'DEF_MOD'
120 | DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:122:9: note: in expansion of macro 'DEF_MOD'
122 | DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[2].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:122:9: note: in expansion of macro 'DEF_MOD'
122 | DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:124:9: note: in expansion of macro 'DEF_MOD'
124 | DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[3].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:124:9: note: in expansion of macro 'DEF_MOD'
124 | DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:126:9: note: in expansion of macro 'DEF_MOD'
126 | DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[4].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:126:9: note: in expansion of macro 'DEF_MOD'
126 | DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:128:9: note: in expansion of macro 'DEF_MOD'
128 | DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[5].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:128:9: note: in expansion of macro 'DEF_MOD'
128 | DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:130:9: note: in expansion of macro 'DEF_MOD'
130 | DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[6].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:130:9: note: in expansion of macro 'DEF_MOD'
130 | DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:132:9: note: in expansion of macro 'DEF_MOD'
132 | DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[7].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:132:9: note: in expansion of macro 'DEF_MOD'
132 | DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:134:9: note: in expansion of macro 'DEF_MOD'
134 | DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[8].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:134:9: note: in expansion of macro 'DEF_MOD'
134 | DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:136:9: note: in expansion of macro 'DEF_MOD'
136 | DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[9].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:136:9: note: in expansion of macro 'DEF_MOD'
136 | DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:138:9: note: in expansion of macro 'DEF_MOD'
138 | DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[10].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:138:9: note: in expansion of macro 'DEF_MOD'
138 | DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:140:9: note: in expansion of macro 'DEF_MOD'
140 | DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[11].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:140:9: note: in expansion of macro 'DEF_MOD'
140 | DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:142:9: note: in expansion of macro 'DEF_MOD'
142 | DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[12].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:142:9: note: in expansion of macro 'DEF_MOD'
142 | DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:144:9: note: in expansion of macro 'DEF_MOD'
144 | DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[13].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:144:9: note: in expansion of macro 'DEF_MOD'
144 | DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:146:9: note: in expansion of macro 'DEF_MOD'
146 | DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[14].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:146:9: note: in expansion of macro 'DEF_MOD'
146 | DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:148:9: note: in expansion of macro 'DEF_MOD'
148 | DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[15].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:148:9: note: in expansion of macro 'DEF_MOD'
148 | DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:150:9: note: in expansion of macro 'DEF_MOD'
150 | DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[16].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:150:9: note: in expansion of macro 'DEF_MOD'
150 | DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:152:9: note: in expansion of macro 'DEF_MOD'
152 | DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[17].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:152:9: note: in expansion of macro 'DEF_MOD'
152 | DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:154:9: note: in expansion of macro 'DEF_MOD'
154 | DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[18].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:154:9: note: in expansion of macro 'DEF_MOD'
154 | DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
| ^~~~~~~
>> drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:156:9: note: in expansion of macro 'DEF_MOD'
156 | DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[19].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:156:9: note: in expansion of macro 'DEF_MOD'
156 | DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:158:9: note: in expansion of macro 'DEF_MOD'
158 | DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[20].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:158:9: note: in expansion of macro 'DEF_MOD'
158 | DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:160:9: note: in expansion of macro 'DEF_MOD'
160 | DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[21].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:160:9: note: in expansion of macro 'DEF_MOD'
160 | DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:162:9: note: in expansion of macro 'DEF_MOD'
162 | DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[22].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:162:9: note: in expansion of macro 'DEF_MOD'
162 | DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:164:9: note: in expansion of macro 'DEF_MOD'
164 | DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[23].mstop_data')
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:164:9: note: in expansion of macro 'DEF_MOD'
164 | DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: error: initializer element is not constant
137 | .mstop_data = (_mstop), \
| ^
drivers/clk/renesas/rzv2h-cpg.h:148:9: note: in expansion of macro 'DEF_MOD_BASE'
148 | DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
| ^~~~~~~~~~~~
drivers/clk/renesas/r9a09g057-cpg.c:166:9: note: in expansion of macro 'DEF_MOD'
166 | DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
| ^~~~~~~
drivers/clk/renesas/rzv2h-cpg.h:137:31: note: (near initialization for 'r9a09g057_mod_clks[24].mstop_data')
137 | .mstop_data = (_mstop), \
vim +/FIELD_PREP_CONST +51 drivers/clk/renesas/rzv2h-cpg.h
48
49 #define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
50 #define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
> 51 #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
52 FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
53 #define BUS_MSTOP_NONE GENMASK(31, 0)
54
55 /**
56 * Definitions of CPG Core Clocks
57 *
58 * These include:
59 * - Clock outputs exported to DT
60 * - External input clocks
61 * - Internal CPG clocks
62 */
63 struct cpg_core_clk {
64 const char *name;
65 unsigned int id;
66 unsigned int parent;
67 unsigned int div;
68 unsigned int mult;
69 unsigned int type;
70 union {
71 unsigned int conf;
72 struct ddiv ddiv;
73 } cfg;
74 const struct clk_div_table *dtable;
75 u32 flag;
76 };
77
78 enum clk_types {
79 /* Generic */
80 CLK_TYPE_IN, /* External Clock Input */
81 CLK_TYPE_FF, /* Fixed Factor Clock */
82 CLK_TYPE_PLL,
83 CLK_TYPE_DDIV, /* Dynamic Switching Divider */
84 };
85
86 /* BIT(31) indicates if CLK1/2 are accessible or not */
87 #define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16)))
88 #define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0)
89 #define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16))
90 #define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4))
91
92 #define DEF_TYPE(_name, _id, _type...) \
93 { .name = _name, .id = _id, .type = _type }
94 #define DEF_BASE(_name, _id, _type, _parent...) \
95 DEF_TYPE(_name, _id, _type, .parent = _parent)
96 #define DEF_PLL(_name, _id, _parent, _conf) \
97 DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.conf = _conf)
98 #define DEF_INPUT(_name, _id) \
99 DEF_TYPE(_name, _id, CLK_TYPE_IN)
100 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \
101 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
102 #define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
103 DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
104 .cfg.ddiv = _ddiv_packed, \
105 .parent = _parent, \
106 .dtable = _dtable, \
107 .flag = CLK_DIVIDER_HIWORD_MASK)
108
109 /**
110 * struct rzv2h_mod_clk - Module Clocks definitions
111 *
112 * @name: handle between common and hardware-specific interfaces
113 * @mstop_data: packed data mstop register offset and mask
114 * @parent: id of parent clock
115 * @critical: flag to indicate the clock is critical
116 * @no_pm: flag to indicate PM is not supported
117 * @on_index: control register index
118 * @on_bit: ON bit
119 * @mon_index: monitor register index
120 * @mon_bit: monitor bit
121 */
122 struct rzv2h_mod_clk {
123 const char *name;
124 u32 mstop_data;
125 u16 parent;
126 bool critical;
127 bool no_pm;
128 u8 on_index;
129 u8 on_bit;
130 s8 mon_index;
131 u8 mon_bit;
132 };
133
134 #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
135 { \
136 .name = (_name), \
> 137 .mstop_data = (_mstop), \
138 .parent = (_parent), \
139 .critical = (_critical), \
140 .no_pm = (_no_pm), \
141 .on_index = (_onindex), \
142 .on_bit = (_onbit), \
143 .mon_index = (_monindex), \
144 .mon_bit = (_monbit), \
145 }
146
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi, On Fri, Jan 3, 2025 at 2:21 AM kernel test robot <lkp@intel.com> wrote: > > Hi Prabhakar, > > kernel test robot noticed the following build errors: > > [auto build test ERROR on geert-renesas-drivers/renesas-clk] > [also build test ERROR on next-20241220] > [cannot apply to linus/master v6.13-rc5] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-rzv2h-Fix-use-after-free-in-MSTOP-refcount-handling/20250103-022238 > base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk > patch link: https://lore.kernel.org/r/20250102181839.352599-4-prabhakar.mahadev-lad.rj%40bp.renesas.com > patch subject: [PATCH v3 3/6] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction > config: sparc-randconfig-002-20250103 (https://download.01.org/0day-ci/archive/20250103/202501030941.vDjx439p-lkp@intel.com/config) > compiler: sparc-linux-gcc (GCC) 14.2.0 > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250103/202501030941.vDjx439p-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot <lkp@intel.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202501030941.vDjx439p-lkp@intel.com/ > > All errors (new ones prefixed by >>): > > In file included from drivers/clk/renesas/r9a09g057-cpg.c:15: > >> drivers/clk/renesas/rzv2h-cpg.h:51:34: error: implicit declaration of function 'FIELD_PREP_CONST' [-Wimplicit-function-declaration] > Thank you for the report, I'll include the required header `#include <linux/bitfield.h>` to fix this issue and send a new version. Cheers, Prabhakar
© 2016 - 2026 Red Hat, Inc.