lvds, lcd, dsi all shares the same GPIO D bank and lvds0
data 3 lines and lvds1 pins are missed, add them.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
index df90c75fb3c5..b97de80ae2f3 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D3P */
SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D3N */
SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D0P */
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D0N */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D1P */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D1N */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D2P */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D2N */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D3P */
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D3N */
SUNXI_FUNCTION(0x4, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
--
2.39.5Hi and thanks for your work!
On Fri 27 Dec 24, 16:37, Parthiban Nallathambi wrote:
> lvds, lcd, dsi all shares the same GPIO D bank and lvds0
> data 3 lines and lvds1 pins are missed, add them.
Would it also make sense to submit device-tree pin definitions here?
Thanks!
Paul
> Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
> ---
> drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> index df90c75fb3c5..b97de80ae2f3 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> @@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = {
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
> + SUNXI_FUNCTION(0x3, "lvds0"), /* D3P */
> SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
> + SUNXI_FUNCTION(0x3, "lvds0"), /* D3N */
> SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D0P */
> SUNXI_FUNCTION(0x4, "spi1"), /* CS */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D0N */
> SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D1P */
> SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D1N */
> SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D2P */
> SUNXI_FUNCTION(0x4, "uart3"), /* TX */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D2N */
> SUNXI_FUNCTION(0x4, "uart3"), /* RX */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */
> SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */
> SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D3P */
> SUNXI_FUNCTION(0x4, "uart4"), /* TX */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D3N */
> SUNXI_FUNCTION(0x4, "uart4"), /* RX */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
>
> --
> 2.39.5
>
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
On 6/25/25 2:16 PM, Paul Kocialkowski wrote:
> Hi and thanks for your work!
>
> On Fri 27 Dec 24, 16:37, Parthiban Nallathambi wrote:
>> lvds, lcd, dsi all shares the same GPIO D bank and lvds0
>> data 3 lines and lvds1 pins are missed, add them.
> Would it also make sense to submit device-tree pin definitions here?
this patch is already merged.
git show --stat cef4f1b5ba99a964cd6dd248bb373520573c972f
commit cef4f1b5ba99a964cd6dd248bb373520573c972f
Author: Parthiban Nallathambi <parthiban@linumiz.com>
Date: Fri Dec 27 16:37:57 2024 +0530
pinctrl: sunxi: add missed lvds pins for a100/a133
lvds, lcd, dsi all shares the same GPIO D bank and lvds0
data 3 lines and lvds1 pins are missed, add them.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Link: https://lore.kernel.org/20241227-a133-display-support-v1-10-13b52f71fb14@linumiz.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
Do you mean the consumer/board devicetree changes?
Thanks,
Parthiban
>
> Thanks!
>
> Paul
On Wed 25 Jun 25, 15:06, Parthiban wrote: > > On 6/25/25 2:16 PM, Paul Kocialkowski wrote: > > Hi and thanks for your work! > > > > On Fri 27 Dec 24, 16:37, Parthiban Nallathambi wrote: > >> lvds, lcd, dsi all shares the same GPIO D bank and lvds0 > >> data 3 lines and lvds1 pins are missed, add them. > > Would it also make sense to submit device-tree pin definitions here? > > this patch is already merged. > git show --stat cef4f1b5ba99a964cd6dd248bb373520573c972f > commit cef4f1b5ba99a964cd6dd248bb373520573c972f > Author: Parthiban Nallathambi <parthiban@linumiz.com> > Date: Fri Dec 27 16:37:57 2024 +0530 > > pinctrl: sunxi: add missed lvds pins for a100/a133 > > lvds, lcd, dsi all shares the same GPIO D bank and lvds0 > data 3 lines and lvds1 pins are missed, add them. > > Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> > Link: https://lore.kernel.org/20241227-a133-display-support-v1-10-13b52f71fb14@linumiz.com > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > Do you mean the consumer/board devicetree changes? I mean the pin definitions for lvds in the sun50i-a100.dtsi device-tree. But maybe you wanted to submit those after the bindings/driver changes are merged? Cheers, Paul -- Paul Kocialkowski, Independent contractor - sys-base - https://www.sys-base.io/ Free software developer - https://www.paulk.fr/ Expert in multimedia, graphics and embedded hardware support with Linux.
On 6/25/25 3:41 PM, Paul Kocialkowski wrote:
> On Wed 25 Jun 25, 15:06, Parthiban wrote:
>>
>> On 6/25/25 2:16 PM, Paul Kocialkowski wrote:
>>> Hi and thanks for your work!
>>>
>>> On Fri 27 Dec 24, 16:37, Parthiban Nallathambi wrote:
>>>> lvds, lcd, dsi all shares the same GPIO D bank and lvds0
>>>> data 3 lines and lvds1 pins are missed, add them.
>>> Would it also make sense to submit device-tree pin definitions here?
>>
>> this patch is already merged.
>> git show --stat cef4f1b5ba99a964cd6dd248bb373520573c972f
>> commit cef4f1b5ba99a964cd6dd248bb373520573c972f
>> Author: Parthiban Nallathambi <parthiban@linumiz.com>
>> Date: Fri Dec 27 16:37:57 2024 +0530
>>
>> pinctrl: sunxi: add missed lvds pins for a100/a133
>>
>> lvds, lcd, dsi all shares the same GPIO D bank and lvds0
>> data 3 lines and lvds1 pins are missed, add them.
>>
>> Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
>> Link: https://lore.kernel.org/20241227-a133-display-support-v1-10-13b52f71fb14@linumiz.com
>> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
>>
>> drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> Do you mean the consumer/board devicetree changes?
>
> I mean the pin definitions for lvds in the sun50i-a100.dtsi device-tree.
>
> But maybe you wanted to submit those after the bindings/driver changes are
> merged?
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-a100-pinctrl";
reg = <0x0300b000 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
lcd_lvds0_pins: lcd-lvds0-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
"PD5", "PD6", "PD7", "PD8", "PD9";
function = "lvds0";
};
lcd_lvds1_pins: lcd-lvds1-pins {
pins = "PD10", "PD11", "PD12", "PD13", "PD14",
"PD15", "PD16", "PD17", "PD18", "PD19";
function = "lvds1";
};
dsi0_pins: dsi0-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
"PD5", "PD6", "PD7", "PD8", "PD9";
function = "dsi0";
};
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
bias-pull-up;
};
It got missed when my email server refused to send all the patches.
I will send the revised full patch series after fixing the comments.
Anyways above are the pin definitions.
Thanks,
Parthiban
https://linumiz.com
https://www.linkedin.com/company/linumiz
Linumiz GmbH
Am Hohen Rott 9, 37170, Uslar
Registergericht: Amtsgericht Göttingen, HRB 207840
Geschäftsführer: Madan Raj Mohanraj
>
> Cheers,
>
> Paul
>
On Fri, Dec 27, 2024 at 12:09 PM Parthiban Nallathambi <parthiban@linumiz.com> wrote: > lvds, lcd, dsi all shares the same GPIO D bank and lvds0 > data 3 lines and lvds1 pins are missed, add them. > > Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> Nobody seems to have any objections about this patch and it seems technically correct so I just applied it to the pin control tree. Yours, Linus Walleij
On Mon, 13 Jan 2025 15:30:24 +0100 Linus Walleij <linus.walleij@linaro.org> wrote: > On Fri, Dec 27, 2024 at 12:09 PM Parthiban Nallathambi > <parthiban@linumiz.com> wrote: > > > lvds, lcd, dsi all shares the same GPIO D bank and lvds0 > > data 3 lines and lvds1 pins are missed, add them. > > > > Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> > > Nobody seems to have any objections about this patch and it seems > technically correct so I just applied it to the pin control tree. I think Parthiban had troubles with his email server, so not the whole series was sent out: https://lore.kernel.org/linux-sunxi/314b6bbe-613e-41a6-955e-50db6e11ef8e@linumiz.com/T/#u At least that put me off from reviewing it in anger. I do have a comment on this, will reply in another mail. So can you hold this patch back still, for now? Cheers, Andre
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