From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

The Last Level Cache is split into many slices, each one of which can
be toggled on or off.

Only certain slices are recommended to be turned on unconditionally,
in order to reach optimal performance/latency/power levels.

Enable WRCACHE on X1 at boot, in accordance with internal
recommendations.

No significant performance difference is expected.

Fixes: b3cf69a43502 ("soc: qcom: llcc: Add configuration data for X1E80100")
Cc: stable@vger.kernel.org
Reviewed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Changes in v3:
- Improve the commit message
- Link to v2: https://lore.kernel.org/r/20241212-topic-llcc_x1e_wrcache-v2-1-e44d3058d06c@oss.qualcomm.com

Changes in v2:
- Cc stable
- Add more context lines
- Pick up r-b
- Link to v1: https://lore.kernel.org/r/20241207-topic-llcc_x1e_wrcache-v1-1-232e6aff49e4@oss.qualcomm.com
---
 drivers/soc/qcom/llcc-qcom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 32c3bc887cefb87c296e3ba67a730c87fa2fa346..1560db00a01248197e5c2936e785a5ea77f74ad8 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -2997,20 +2997,21 @@ static const struct llcc_slice_config x1e80100_data[] = {
 		.bonus_ways = 0xfff,
 		.cache_mode = 0,
 	}, {
 		.usecase_id = LLCC_WRCACHE,
 		.slice_id = 31,
 		.max_cap = 1024,
 		.priority = 1,
 		.fixed_size = true,
 		.bonus_ways = 0xfff,
 		.cache_mode = 0,
+		.activate_on_init = true,
 	}, {
 		.usecase_id = LLCC_CAMEXP0,
 		.slice_id = 4,
 		.max_cap = 256,
 		.priority = 4,
 		.fixed_size = true,
 		.bonus_ways = 0x3,
 		.cache_mode = 0,
 	}, {
 		.usecase_id = LLCC_CAMEXP1,

---
base-commit: 3e42dc9229c5950e84b1ed705f94ed75ed208228
change-id: 20241207-topic-llcc_x1e_wrcache-647070e2d130

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

On Thu, 19 Dec 2024 19:53:29 +0100, Konrad Dybcio wrote:
> The Last Level Cache is split into many slices, each one of which can
> be toggled on or off.
> 
> Only certain slices are recommended to be turned on unconditionally,
> in order to reach optimal performance/latency/power levels.
> 
> Enable WRCACHE on X1 at boot, in accordance with internal
> recommendations.
> 
> [...]

Applied, thanks!

[1/1] soc: qcom: llcc: Enable LLCC_WRCACHE at boot on X1
      commit: 35d8bc131de0f0f280f0db42499512d79f05f456

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

On Thu, Dec 19, 2024 at 07:53:29PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> The Last Level Cache is split into many slices, each one of which can
> be toggled on or off.
> 
> Only certain slices are recommended to be turned on unconditionally,
> in order to reach optimal performance/latency/power levels.
> 
> Enable WRCACHE on X1 at boot, in accordance with internal
> recommendations.

Thanks for the update. Can you say something about what WRCACHE is used
for as well?

> No significant performance difference is expected.

This matches my findings (and it seems the slice has not been left
enabled by the boot firmware).

> Fixes: b3cf69a43502 ("soc: qcom: llcc: Add configuration data for X1E80100")
> Cc: stable@vger.kernel.org
> Reviewed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>

Johan