[v2] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

Posted by Lijuan Gao 12 months ago

The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed
through the GPIO framework. It is expected to be wired to the reset pin
of the primary UFS memory so that the UFS driver can toggle it.

The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The
QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to
124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
gpio-rangs to 134.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
Changes in v2:
- Update the introductory information in the cover letter
- Update the commit message
- Update the title of the TLMM driver patch
- Link to v1: https://lore.kernel.org/r/20241212-correct_gpio_ranges-v1-0-c5f20d61882f@quicinc.com

---
Lijuan Gao (6):
      dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
      dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
      pinctrl: qcom: correct the ngpios entry for QCS615
      pinctrl: qcom: correct the ngpios entry for QCS8300
      arm64: dts: qcom: correct gpio-ranges for QCS615
      arm64: dts: qcom: correct gpio-ranges for QCS8300

 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml  | 2 +-
 Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
 arch/arm64/boot/dts/qcom/qcs615.dtsi                             | 2 +-
 arch/arm64/boot/dts/qcom/qcs8300.dtsi                            | 2 +-
 drivers/pinctrl/qcom/pinctrl-qcs615.c                            | 2 +-
 drivers/pinctrl/qcom/pinctrl-qcs8300.c                           | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)
---
base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07
change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7

Best regards,
-- 
Lijuan Gao <quic_lijuang@quicinc.com>

Re: [PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

Posted by Linus Walleij 12 months ago

Hi Lijuan,

thanks for your patches!

On Thu, Dec 19, 2024 at 9:00 AM Lijuan Gao <quic_lijuang@quicinc.com> wrote:

> The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed
> through the GPIO framework. It is expected to be wired to the reset pin
> of the primary UFS memory so that the UFS driver can toggle it.
>
> The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The
> QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to
> 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
> gpio-rangs to 134.
(...)
> Lijuan Gao (6):
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
>       pinctrl: qcom: correct the ngpios entry for QCS615
>       pinctrl: qcom: correct the ngpios entry for QCS8300

I'm planning to apply these 4 after v3 arrives with the collected ACKs etc.

Yours,
Linus Walleij

Re: (subset) [PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

Posted by Bjorn Andersson 11 months, 2 weeks ago

On Thu, 19 Dec 2024 15:59:42 +0800, Lijuan Gao wrote:
> The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed
> through the GPIO framework. It is expected to be wired to the reset pin
> of the primary UFS memory so that the UFS driver can toggle it.
> 
> The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The
> QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to
> 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
> gpio-rangs to 134.
> 
> [...]

Applied, thanks!

[5/6] arm64: dts: qcom: correct gpio-ranges for QCS615
      commit: 80c82827327d80bde8fc96ebd4e637d0454062db
[6/6] arm64: dts: qcom: correct gpio-ranges for QCS8300
      commit: c57c39ee522d873db2cb23486581a8269c389cfe

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>