[v1] Add SYS and GIC clock entries for RZ/V2H(P) SoC

[PATCH 0/5] Add SYS and GIC clock entries for RZ/V2H(P) SoC

Prabhakar posted 5 patches 12 months ago

Diff against v2
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drivers/clk/renesas/r9a09g057-cpg.c |  5 +++++
drivers/clk/renesas/rzv2h-cpg.c     | 15 +++++++++++----
drivers/clk/renesas/rzv2h-cpg.h     |  8 ++++----
3 files changed, 20 insertions(+), 8 deletions(-)

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[PATCH 0/5] Add SYS and GIC clock entries for RZ/V2H(P) SoC

Posted by Prabhakar 12 months ago

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds support for clock and reset entries for GIC and
SYS, along with some cleanup and fixes to the CPG family driver.

Cheers,
Prabhakar

Lad Prabhakar (5):
  clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling
  clk: renesas: rzv2h: Relocate MSTOP-related macros to the family
    driver
  clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction
  clk: renesas: r9a09g057: Add reset entry for SYS
  clk: renesas: r9a09g057: Add clock and reset entries for GIC

 drivers/clk/renesas/r9a09g057-cpg.c |  5 +++++
 drivers/clk/renesas/rzv2h-cpg.c     | 15 +++++++++++----
 drivers/clk/renesas/rzv2h-cpg.h     |  8 ++++----
 3 files changed, 20 insertions(+), 8 deletions(-)

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2.43.0