Add PM8775 ADC5 GEN3 Channel info and bindings for the MBG Temp
alarm peripheral found on PM8775 pmic.
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
.../bindings/thermal/qcom-spmi-mbg-tm.yaml | 86 ++++++++++++++++++++++
.../iio/adc/qcom,spmi-adc5-gen3-pm8775.h | 41 +++++++++++
2 files changed, 127 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..909373eb758e4a8b7c2bbd0022c56ab2e823ca13
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qcom-spmi-mbg-tm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SPMI PMIC MBG Thermal Monitoring
+
+maintainers:
+ - Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
+
+description:
+ Qualcomm's MBG(Master Bandgap) temperature alarm monitors the die
+ temperature and generates an interrupt if the PMIC die temperature is
+ over a set of programmable temperature thresholds. It allows monitoring
+ for both hot and cold, LVL1 and LVL2 thresholds, which makes it different
+ from the existing temp alarm peripheral. The interrupt comes over SPMI
+ and the MBG's fault status register gives details to understand whether
+ it is a hot/cold and LVL1/LVL2 violation.
+
+allOf:
+ - $ref: thermal-sensor.yaml#
+
+properties:
+ compatible:
+ const: qcom,spmi-pm8775-mbg-tm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ io-channels:
+ items:
+ - description: ADC channel, which reports chip die temperature.
+
+ io-channel-names:
+ const: thermal
+
+ "#thermal-sensor-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - io-channels
+ - io-channel-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h>
+
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmm8654au_0_tz: temperature-sensor@d700 {
+ compatible = "qcom,spmi-pm8775-mbg-tm";
+ reg = <0xd700>;
+ interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pm8775_1_adc PM8775_ADC5_GEN3_DIE_TEMP(1)>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ thermal-zones {
+ pm8775-mbg0-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmm8654au_0_tz>;
+
+ trips {
+ trip0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+...
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h
new file mode 100644
index 0000000000000000000000000000000000000000..33f5454367777b10fda248476a0abd17da86ecf6
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+#define PM8775_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
+#define PM8775_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
+#define PM8775_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8775_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PM8775_ADC5_GEN3_AMUX1_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM)
+#define PM8775_ADC5_GEN3_AMUX2_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM)
+#define PM8775_ADC5_GEN3_AMUX3_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM)
+#define PM8775_ADC5_GEN3_AMUX4_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM)
+#define PM8775_ADC5_GEN3_AMUX5_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM)
+#define PM8775_ADC5_GEN3_AMUX6_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM)
+#define PM8775_ADC5_GEN3_AMUX1_GPIO9(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO)
+#define PM8775_ADC5_GEN3_AMUX2_GPIO10(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO)
+#define PM8775_ADC5_GEN3_AMUX3_GPIO11(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO)
+#define PM8775_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO)
+
+/* 100k pull-up2 */
+#define PM8775_ADC5_GEN3_AMUX1_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX2_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX3_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX4_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX5_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX6_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX1_GPIO9_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX2_GPIO10_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX3_GPIO11_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU)
+
+#define PM8775_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H */
--
2.25.1On 12.12.2024 5:11 PM, Satya Priya Kakitapalli wrote: > Add PM8775 ADC5 GEN3 Channel info and bindings for the MBG Temp > alarm peripheral found on PM8775 pmic. > > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> > --- > .../bindings/thermal/qcom-spmi-mbg-tm.yaml | 86 ++++++++++++++++++++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h | 41 +++++++++++ > 2 files changed, 127 insertions(+) > > diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..909373eb758e4a8b7c2bbd0022c56ab2e823ca13 > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml > @@ -0,0 +1,86 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/thermal/qcom-spmi-mbg-tm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Technologies, Inc. SPMI PMIC MBG Thermal Monitoring > + > +maintainers: > + - Satya Priya Kakitapalli <quic_skakitap@quicinc.com> > + > +description: > + Qualcomm's MBG(Master Bandgap) temperature alarm monitors the die > + temperature and generates an interrupt if the PMIC die temperature is > + over a set of programmable temperature thresholds. It allows monitoring > + for both hot and cold, LVL1 and LVL2 thresholds, which makes it different > + from the existing temp alarm peripheral. The interrupt comes over SPMI > + and the MBG's fault status register gives details to understand whether > + it is a hot/cold and LVL1/LVL2 violation. > + > +allOf: > + - $ref: thermal-sensor.yaml# > + > +properties: > + compatible: > + const: qcom,spmi-pm8775-mbg-tm The bus the chip is connected over shouldn't be part of the compatible Konrad
On Thu, Dec 12, 2024 at 09:41:20PM +0530, Satya Priya Kakitapalli wrote:
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - io-channels
> + - io-channel-names
Binding looks ok, but this wasn't tested due to unneeded dependency.
Please decouple from dependency, so automation can properly test it.
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h>
> +
> + pmic {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pmm8654au_0_tz: temperature-sensor@d700 {
Drop label.
> + compatible = "qcom,spmi-pm8775-mbg-tm";
> + reg = <0xd700>;
> + interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
> + io-channels = <&pm8775_1_adc PM8775_ADC5_GEN3_DIE_TEMP(1)>;
> + io-channel-names = "thermal";
> + #thermal-sensor-cells = <0>;
> + };
> + };
> +
> + thermal-zones {
> + pm8775-mbg0-thermal {
Drop the nodes, not related.
Best regards,
Krzysztof
On Thu, 12 Dec 2024 21:41:20 +0530, Satya Priya Kakitapalli wrote:
> Add PM8775 ADC5 GEN3 Channel info and bindings for the MBG Temp
> alarm peripheral found on PM8775 pmic.
>
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---
> .../bindings/thermal/qcom-spmi-mbg-tm.yaml | 86 ++++++++++++++++++++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h | 41 +++++++++++
> 2 files changed, 127 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
In file included from Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.example.dts:25:
./scripts/dtc/include-prefixes/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h:9:10: fatal error: dt-bindings/iio/adc/qcom,spmi-vadc.h: No such file or directory
9 | #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.dtbs:131: Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1506: dt_binding_check] Error 2
make: *** [Makefile:251: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241212-mbg-v2-support-v2-1-3249a4339b6e@quicinc.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
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