Add "capacity-dmips-mhz" and "dynamic-power-coefficient" to the QCS615 SoC.
They are used to build the energy model, which in turn is used by EAS to
take placement decisions.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index c0e4b376a1c6..5d2034a10f2e 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -29,6 +29,8 @@ cpu0: cpu@0 {
 			enable-method = "psci";
 			power-domains = <&cpu_pd0>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_0>;
 			#cooling-cells = <2>;
 
@@ -47,6 +49,8 @@ cpu1: cpu@100 {
 			enable-method = "psci";
 			power-domains = <&cpu_pd1>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_100>;
 
 			l2_100: l2-cache {
@@ -64,6 +68,8 @@ cpu2: cpu@200 {
 			enable-method = "psci";
 			power-domains = <&cpu_pd2>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_200>;
 
 			l2_200: l2-cache {
@@ -81,6 +87,8 @@ cpu3: cpu@300 {
 			enable-method = "psci";
 			power-domains = <&cpu_pd3>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_300>;
 
 			l2_300: l2-cache {
@@ -98,6 +106,8 @@ cpu4: cpu@400 {
 			enable-method = "psci";
 			power-domains = <&cpu_pd4>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_400>;
 
 			l2_400: l2-cache {
@@ -115,6 +125,8 @@ cpu5: cpu@500 {
 			enable-method = "psci";
 			power-domains = <&cpu_pd5>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_500>;
 
 			l2_500: l2-cache {
@@ -132,6 +144,8 @@ cpu6: cpu@600 {
 			enable-method = "psci";
 			power-domains = <&cpu_pd6>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1740>;
+			dynamic-power-coefficient = <404>;
 			next-level-cache = <&l2_600>;
 			#cooling-cells = <2>;
 
@@ -150,6 +164,8 @@ cpu7: cpu@700 {
 			enable-method = "psci";
 			power-domains = <&cpu_pd7>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1740>;
+			dynamic-power-coefficient = <404>;
 			next-level-cache = <&l2_700>;
 
 			l2_700: l2-cache {

---
base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07
change-id: 20241211-add_cpu_capacity_and_dpc_properties-8d6627dbfb09

Best regards,
-- 
Lijuan Gao <quic_lijuang@quicinc.com>

On Wed, 11 Dec 2024 17:35:46 +0800, Lijuan Gao wrote:
> Add "capacity-dmips-mhz" and "dynamic-power-coefficient" to the QCS615 SoC.
> They are used to build the energy model, which in turn is used by EAS to
> take placement decisions.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: qcs615: Add CPU capacity and DPC properties
      commit: 82db707eb97d96f6460730a65be9cb2f9b3a4959

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

On 11.12.2024 10:35 AM, Lijuan Gao wrote:
> Add "capacity-dmips-mhz" and "dynamic-power-coefficient" to the QCS615 SoC.
> They are used to build the energy model, which in turn is used by EAS to
> take placement decisions.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad