[v2] KVM: arm64: Enable FGU (Fine Grained Undefined) for FEAT_FGT2 registers

[PATCH V2 03/46] arm64/sysreg: Update register fields for ID_AA64PFR0_EL1

Posted by Anshuman Khandual 1 year, 2 months ago

This updates ID_AA64PFR0_EL1.RAS and ID_AA64PFR0_EL1.RME register fields as
per the definitions based on DDI0601 2024-09.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index b5bda7c94689..59351931d907 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -873,6 +873,8 @@ EndEnum
 UnsignedEnum	55:52	RME
 	0b0000	NI
 	0b0001	IMP
+	0b0010	GPC2
+	0b0011	GPC3
 EndEnum
 UnsignedEnum	51:48	DIT
 	0b0000	NI
@@ -899,6 +901,7 @@ UnsignedEnum	31:28	RAS
 	0b0000	NI
 	0b0001	IMP
 	0b0010	V1P1
+	0b0011	V2
 EndEnum
 UnsignedEnum	27:24	GIC
 	0b0000	NI
-- 
2.25.1

Re: [PATCH V2 03/46] arm64/sysreg: Update register fields for ID_AA64PFR0_EL1

Posted by Eric Auger 1 year, 1 month ago


On 12/10/24 06:52, Anshuman Khandual wrote:
> This updates ID_AA64PFR0_EL1.RAS and ID_AA64PFR0_EL1.RME register fields as
> per the definitions based on DDI0601 2024-09.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
> ---
>  arch/arm64/tools/sysreg | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index b5bda7c94689..59351931d907 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -873,6 +873,8 @@ EndEnum
>  UnsignedEnum	55:52	RME
>  	0b0000	NI
>  	0b0001	IMP
> +	0b0010	GPC2
> +	0b0011	GPC3
>  EndEnum
>  UnsignedEnum	51:48	DIT
>  	0b0000	NI
> @@ -899,6 +901,7 @@ UnsignedEnum	31:28	RAS
>  	0b0000	NI
>  	0b0001	IMP
>  	0b0010	V1P1
> +	0b0011	V2
>  EndEnum
>  UnsignedEnum	27:24	GIC
>  	0b0000	NI

Re: [PATCH V2 03/46] arm64/sysreg: Update register fields for ID_AA64PFR0_EL1

Posted by Mark Brown 1 year, 1 month ago

On Tue, Dec 10, 2024 at 11:22:28AM +0530, Anshuman Khandual wrote:
> This updates ID_AA64PFR0_EL1.RAS and ID_AA64PFR0_EL1.RME register fields as
> per the definitions based on DDI0601 2024-09.

Reviewed-by: Mark Brown <broonie@kernel.org>