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[PATCH 0/5] soc: renesas: Add system controller support for RZ/G3E SoC

John Madieu posted 5 patches 1 year ago
There is a newer version of this series
.../soc/renesas/renesas,r9a09g057-sys.yaml    |  8 ++-
arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  7 ++
arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |  2 +-
drivers/soc/renesas/Kconfig                   |  6 ++
drivers/soc/renesas/Makefile                  |  1 +
drivers/soc/renesas/r9a09g047-sysc.c          | 70 +++++++++++++++++++
drivers/soc/renesas/rz-sysc.c                 | 44 ++++++++----
drivers/soc/renesas/rz-sysc.h                 |  7 ++
8 files changed, 128 insertions(+), 17 deletions(-)
create mode 100644 drivers/soc/renesas/r9a09g047-sysc.c
[PATCH 0/5] soc: renesas: Add system controller support for RZ/G3E SoC
Posted by John Madieu 1 year ago 
This patch series adds support for the RZ/G3E system controller and extends
the existing RZ/V2H(P) system controller to support syscon. The RZ/G3E
system controller allows detecting various SoC features like core count,
NPU availability, and CA55 PLL configuration.

Key features:
- Syscon support for both RZ/V2H and RZ/G3E system controllers
- Detection of quad/dual core configuration
- Detection of Ethos-U55 NPU presence
- Validation of CA55 PLL frequency setting
- SoC-specific extended identification through callbacks

This patch series depends upon [1] and [2].

Tested:
- Example of SoC detection:
[    0.065608] renesas-rz-sysc 10430000.system-controller: Detected Renesas Quad Core RZ/G3E r9a09g047 Rev 0  with Ethos-U55
- Example of PLL misconfiguration warning:
 [    0.065616] renesas-rz-sysc 10430000.system-controller: CA55 PLL is not set to 1.7GHz

[1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=914097
[2] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=912697

John Madieu (5):
  dt-bindings: arm: renesas: Add syscon compatibility to RZ/V2H(P) SYS
    Controller
  dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
  soc: renesas: rz-sysc: Add support for RZ/G3E family
  arm64: dts: renesas: r9a09g047: add sys node
  arm64: dts: renesas: r9a09g057: Add syscon compatibility to sys node

 .../soc/renesas/renesas,r9a09g057-sys.yaml    |  8 ++-
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  7 ++
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |  2 +-
 drivers/soc/renesas/Kconfig                   |  6 ++
 drivers/soc/renesas/Makefile                  |  1 +
 drivers/soc/renesas/r9a09g047-sysc.c          | 70 +++++++++++++++++++
 drivers/soc/renesas/rz-sysc.c                 | 44 ++++++++----
 drivers/soc/renesas/rz-sysc.h                 |  7 ++
 8 files changed, 128 insertions(+), 17 deletions(-)
 create mode 100644 drivers/soc/renesas/r9a09g047-sysc.c

-- 
2.25.1
[PATCH v2 0/4] soc: renesas: Add system controller support for RZ/G3E SoC
Posted by John Madieu 11 months, 2 weeks ago 
This patch series adds support for the RZ/G3E system controller and extends
the existing RZ/V2H(P) system controller to support syscon. The RZ/G3E
system controller allows detecting various SoC features like core count,
NPU availability, and CA55 PLL configuration.

Changes in v2:
- Fixed code style issues in rz-sysc.c and r9a09g047-sysc.c
- Fixed device tree documentation, getting rid of syscon compatible string
- Handled non signal-aware readable/writeable regmap callback
- Consolidated common code between RZ/V2H and RZ/G3E drivers
- Moved SoC ID detection from the compatible string fix into a new patch

Key features:
- Syscon support for both RZ/V2H and RZ/G3E system controllers
- Detection of quad/dual core configuration
- Detection of Ethos-U55 NPU presence
- Validation of CA55 PLL frequency setting
- SoC-specific extended identification through callbacks

This patch series depends upon [1], [2], and [3].

Tested:
- Example of SoC detection:
[    0.065608] renesas-rz-sysc 10430000.system-controller: Detected Renesas 
Quad Core RZ/G3E r9a09g047 Rev 0  with Ethos-U55

- Example of PLL misconfiguration warning:
[    0.065616] renesas-rz-sysc 10430000.system-controller: CA55 PLL is not 
set to 1.7GHz

[1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=914097
[2] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=912455
[3] https://lore.kernel.org/lkml/Z2HTAJmBeIUlWysh@google.com/T/

John Madieu (4):
  dt-bindings: soc: renesas: Add RZ/G3E variant SYS bindings
  soc: renesas: rz-sysc: Fix SoC ID string extraction
  soc: renesas: rz-sysc: Add support for RZ/G3E family
  arm64: dts: renesas: r9a09g047: add sys node

 .../soc/renesas/renesas,r9a09g057-sys.yaml    |  5 +-
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  7 ++
 drivers/soc/renesas/Kconfig                   |  6 ++
 drivers/soc/renesas/Makefile                  |  1 +
 drivers/soc/renesas/r9a09g047-sysc.c          | 73 +++++++++++++++++++
 drivers/soc/renesas/rz-sysc.c                 | 24 +++++-
 drivers/soc/renesas/rz-sysc.h                 |  6 ++
 7 files changed, 118 insertions(+), 4 deletions(-)
 create mode 100644 drivers/soc/renesas/r9a09g047-sysc.c

-- 
2.25.1
[PATCH v2 1/4] dt-bindings: soc: renesas: Add RZ/G3E variant SYS bindings
Posted by John Madieu 11 months, 2 weeks ago 
Add RZ/G3E (R9A09G047) variant to the existing RZ/V2H System
Controller (SYS) binding as both IPs are compatible.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
 - v1 -> v2: Do not rely on syscon compatible string anymore

Notes:
    v1: Acked-by: Rob Herring (Arm) <robh@kernel.org>
    v1: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
    v2: Tags dropped due to small changes in compatible property structure.

 .../bindings/soc/renesas/renesas,r9a09g057-sys.yaml          | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
index ebbf0c9109ce..e0f7503a9f35 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
@@ -22,7 +22,10 @@ description: |
 
 properties:
   compatible:
-    const: renesas,r9a09g057-sys
+    items:
+      - enum:
+          - renesas,r9a09g047-sys # RZ/G3E
+          - renesas,r9a09g057-sys # RZ/V2H
 
   reg:
     maxItems: 1
-- 
2.25.1
Re: [PATCH v2 1/4] dt-bindings: soc: renesas: Add RZ/G3E variant SYS bindings
Posted by Rob Herring (Arm) 11 months, 2 weeks ago 
On Wed, 01 Jan 2025 17:33:41 +0100, John Madieu wrote:
> Add RZ/G3E (R9A09G047) variant to the existing RZ/V2H System
> Controller (SYS) binding as both IPs are compatible.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
> Changes:
>  - v1 -> v2: Do not rely on syscon compatible string anymore
> 
> Notes:
>     v1: Acked-by: Rob Herring (Arm) <robh@kernel.org>
>     v1: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>     v2: Tags dropped due to small changes in compatible property structure.
> 
>  .../bindings/soc/renesas/renesas,r9a09g057-sys.yaml          | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
[PATCH v2 2/4] soc: renesas: rz-sysc: Fix SoC ID string extraction
Posted by John Madieu 11 months, 2 weeks ago 
Fix string length calculation when extracting the SoC ID from the compatible
string. Add +1 to the size calculation to ensure proper string termination when
copying with strncpy().

This prevents potential string trunctation when processing the device tree
compatible string to identify the SoC.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
New patch introduced in v2, targetting specific fix.

 drivers/soc/renesas/rz-sysc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c
index d34d295831b8..e472fda3995b 100644
--- a/drivers/soc/renesas/rz-sysc.c
+++ b/drivers/soc/renesas/rz-sysc.c
@@ -231,7 +231,7 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat
 
 	soc_id_start = strchr(match->compatible, ',') + 1;
 	soc_id_end = strchr(match->compatible, '-');
-	size = soc_id_end - soc_id_start;
+	size = soc_id_end - soc_id_start + 1;
 	if (size > 32)
 		size = 32;
 	strscpy(soc_id, soc_id_start, size);
-- 
2.25.1
Re: [PATCH v2 2/4] soc: renesas: rz-sysc: Fix SoC ID string extraction
Posted by Geert Uytterhoeven 11 months, 2 weeks ago 
Hi John,

On Wed, Jan 1, 2025 at 5:34 PM John Madieu
<john.madieu.xa@bp.renesas.com> wrote:
> Fix string length calculation when extracting the SoC ID from the compatible
> string. Add +1 to the size calculation to ensure proper string termination when
> copying with strncpy().
>
> This prevents potential string trunctation when processing the device tree
> compatible string to identify the SoC.
>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
> New patch introduced in v2, targetting specific fix.

Thanks for your patch!

> --- a/drivers/soc/renesas/rz-sysc.c
> +++ b/drivers/soc/renesas/rz-sysc.c
> @@ -231,7 +231,7 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat
>
>         soc_id_start = strchr(match->compatible, ',') + 1;
>         soc_id_end = strchr(match->compatible, '-');
> -       size = soc_id_end - soc_id_start;
> +       size = soc_id_end - soc_id_start + 1;
>         if (size > 32)
>                 size = 32;
>         strscpy(soc_id, soc_id_start, size);

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

As the code fixed was introduced by a patch[1] that has not been
accepted yet, this fix should be incorporated into the original patch
(together with other fixes according to review comments).

[1] "[PATCH v2 04/15] soc: renesas: rz-sysc: Add SoC detection support"
https://lore.kernel.org/linux-renesas-soc/20241126092050.1825607-5-claudiu.beznea.uj@bp.renesas.com

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
[PATCH v2 3/4] soc: renesas: rz-sysc: Add support for RZ/G3E family
Posted by John Madieu 11 months, 2 weeks ago 
Add SoC detection support for RZ/G3E SoC. Also add support for detecting the
number of cores and ETHOS-U55 NPU and also detect PLL mismatch for SW settings
other than 1.7GHz.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes in v2:
 - Group bitfields ordered by registers
 - Rename SoC-specific callback field to 'print_id'
 - Explicitely select 'MFD_SYSCON' config option
 - Do not rely on 'syscon'-compatible probing anymore.


 drivers/soc/renesas/Kconfig          |  6 +++
 drivers/soc/renesas/Makefile         |  1 +
 drivers/soc/renesas/r9a09g047-sysc.c | 73 ++++++++++++++++++++++++++++
 drivers/soc/renesas/rz-sysc.c        | 22 ++++++++-
 drivers/soc/renesas/rz-sysc.h        |  6 +++
 5 files changed, 106 insertions(+), 2 deletions(-)
 create mode 100644 drivers/soc/renesas/r9a09g047-sysc.c

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index a792a3e915fe..33759f69c37c 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -348,6 +348,7 @@ config ARCH_R9A09G011
 
 config ARCH_R9A09G047
 	bool "ARM64 Platform support for RZ/G3E"
+	select SYSC_R9A09G047
 	help
 	  This enables support for the Renesas RZ/G3E SoC variants.
 
@@ -386,9 +387,14 @@ config RST_RCAR
 
 config SYSC_RZ
 	bool "System controller for RZ SoCs" if COMPILE_TEST
+	select MFD_SYSCON
 
 config SYSC_R9A08G045
 	bool "Renesas RZ/G3S System controller support" if COMPILE_TEST
 	select SYSC_RZ
 
+config SYSC_R9A09G047
+	bool "Renesas RZ/G3E System controller support" if COMPILE_TEST
+	select SYSC_RZ
+
 endif # SOC_RENESAS
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 8cd139b3dd0a..3256706112d9 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -7,6 +7,7 @@ ifdef CONFIG_SMP
 obj-$(CONFIG_ARCH_R9A06G032)	+= r9a06g032-smp.o
 endif
 obj-$(CONFIG_SYSC_R9A08G045)	+= r9a08g045-sysc.o
+obj-$(CONFIG_SYSC_R9A09G047)	+= r9a09g047-sysc.o
 
 # Family
 obj-$(CONFIG_PWC_RZV2M)		+= pwc-rzv2m.o
diff --git a/drivers/soc/renesas/r9a09g047-sysc.c b/drivers/soc/renesas/r9a09g047-sysc.c
new file mode 100644
index 000000000000..3ad6057f9196
--- /dev/null
+++ b/drivers/soc/renesas/r9a09g047-sysc.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G3E System controller driver
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include "rz-sysc.h"
+
+/* Register Offsets */
+#define SYS_LSI_DEVID		0x304
+#define SYS_LSI_DEVID_REV	GENMASK(31, 28)
+#define SYS_LSI_DEVID_SPECIFIC	GENMASK(27, 0)
+#define SYS_LSI_MODE		0x300
+/*
+ * BOOTPLLCA[1:0]
+ *	    [0,0] => 1.1GHZ
+ *	    [0,1] => 1.5GHZ
+ *	    [1,0] => 1.6GHZ
+ *	    [1,1] => 1.7GHZ
+ */
+#define SYS_LSI_MODE_STAT_BOOTPLLCA55	GENMASK(12, 11)
+#define SYS_LSI_MODE_CA55_1_7GHZ	0x3
+#define SYS_LSI_PRR			0x308
+#define SYS_LSI_PRR_CA55_DIS		BIT(8)
+#define SYS_LSI_PRR_NPU_DIS		BIT(1)
+#define SYS_MAX_REG			0x170c
+
+
+static void rzg3e_sysc_print_id(struct device *dev,
+				void __iomem *sysc_base,
+				struct soc_device_attribute *soc_dev_attr)
+{
+	bool is_quad_core, npu_enabled;
+	u32 prr_val, mode_val;
+
+	prr_val = readl(sysc_base + SYS_LSI_PRR);
+	mode_val = readl(sysc_base + SYS_LSI_MODE);
+
+	/* Check CPU and NPU configuration */
+	is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
+	npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
+
+	dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n",
+		 is_quad_core ? "Quad" : "Dual",
+		 soc_dev_attr->family,
+		 soc_dev_attr->soc_id,
+		 soc_dev_attr->revision,
+		 npu_enabled ? " with Ethos-U55" : "");
+
+	/* Check CA55 PLL configuration */
+	if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
+		dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
+}
+
+static const struct rz_sysc_soc_id_init_data rzg3e_sysc_soc_id_init_data __initconst = {
+	.family = "RZ/G3E",
+	.id = 0x8679447,
+	.offset = SYS_LSI_DEVID,
+	.revision_mask = SYS_LSI_DEVID_REV,
+	.specific_id_mask = SYS_LSI_DEVID_SPECIFIC,
+	.print_id = rzg3e_sysc_print_id,
+};
+
+const struct rz_sysc_init_data rzg3e_sysc_init_data = {
+	.soc_id_init_data = &rzg3e_sysc_soc_id_init_data,
+	.max_register_offset = SYS_MAX_REG,
+};
diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c
index e472fda3995b..6a33807e925a 100644
--- a/drivers/soc/renesas/rz-sysc.c
+++ b/drivers/soc/renesas/rz-sysc.c
@@ -130,6 +130,10 @@ static bool rz_sysc_writeable_reg(struct device *dev, unsigned int off)
 	struct rz_sysc *sysc = dev_get_drvdata(dev);
 	struct rz_sysc_signal *signal;
 
+	/* Fast path if not signal-aware */
+	if (!sysc->num_signals)
+		return true;
+
 	/* Any register containing a signal is writeable. */
 	signal = rz_sysc_off_to_signal(sysc, off, 0);
 	if (signal)
@@ -143,6 +147,10 @@ static bool rz_sysc_readable_reg(struct device *dev, unsigned int off)
 	struct rz_sysc *sysc = dev_get_drvdata(dev);
 	struct rz_sysc_signal *signal;
 
+	/* Fast path if not signal-aware */
+	if (!sysc->num_signals)
+		return true;
+
 	/* Any register containing a signal is readable. */
 	signal = rz_sysc_off_to_signal(sysc, off, 0);
 	if (signal)
@@ -257,8 +265,15 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat
 		return -ENODEV;
 	}
 
-	dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", soc_dev_attr->family,
-		 soc_dev_attr->soc_id, soc_dev_attr->revision);
+	/* Try to call SoC-specific device identification */
+	if (soc_data->print_id) {
+		soc_data->print_id(sysc->dev, sysc->base, soc_dev_attr);
+	} else {
+		dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n",
+			 soc_dev_attr->family,
+			 soc_dev_attr->soc_id,
+			 soc_dev_attr->revision);
+	}
 
 	soc_dev = soc_device_register(soc_dev_attr);
 	if (IS_ERR(soc_dev))
@@ -283,6 +298,9 @@ static struct regmap_config rz_sysc_regmap = {
 static const struct of_device_id rz_sysc_match[] = {
 #ifdef CONFIG_SYSC_R9A08G045
 	{ .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data },
+#endif
+#ifdef CONFIG_SYSC_R9A09G047
+	{ .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sysc_init_data },
 #endif
 	{ }
 };
diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h
index babca9c743c7..2c92b252b40c 100644
--- a/drivers/soc/renesas/rz-sysc.h
+++ b/drivers/soc/renesas/rz-sysc.h
@@ -8,7 +8,9 @@
 #ifndef __SOC_RENESAS_RZ_SYSC_H__
 #define __SOC_RENESAS_RZ_SYSC_H__
 
+#include <linux/device.h>
 #include <linux/refcount.h>
+#include <linux/sys_soc.h>
 #include <linux/types.h>
 
 /**
@@ -42,6 +44,7 @@ struct rz_sysc_signal {
  * @offset: SYSC SoC ID register offset
  * @revision_mask: SYSC SoC ID revision mask
  * @specific_id_mask: SYSC SoC ID specific ID mask
+ * @print_id: SoC-specific extended device identification
  */
 struct rz_sysc_soc_id_init_data {
 	const char * const family;
@@ -49,6 +52,8 @@ struct rz_sysc_soc_id_init_data {
 	u32 offset;
 	u32 revision_mask;
 	u32 specific_id_mask;
+	void (*print_id)(struct device *dev, void __iomem *sysc_base,
+			 struct soc_device_attribute *soc_dev_attr);
 };
 
 /**
@@ -65,6 +70,7 @@ struct rz_sysc_init_data {
 	u32 max_register_offset;
 };
 
+extern const struct rz_sysc_init_data rzg3e_sysc_init_data;
 extern const struct rz_sysc_init_data rzg3s_sysc_init_data;
 
 #endif /* __SOC_RENESAS_RZ_SYSC_H__ */
-- 
2.25.1
[PATCH v2 4/4] arm64: dts: renesas: r9a09g047: add sys node
Posted by John Madieu 11 months, 2 weeks ago 
Add system controller node to RZ/G3E (R9A09G047) SoC DTSI.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index b73daf43683f..e87521cf9a0b 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -162,6 +162,13 @@ cpg: clock-controller@10420000 {
 			#power-domain-cells = <0>;
 		};
 
+		sys: system-controller@10430000 {
+			compatible = "renesas,r9a09g047-sys";
+			reg = <0 0x10430000 0 0x10000>;
+			clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>;
+			resets = <&cpg 0x30>;
+		};
+
 		ostm0: timer@11800000 {
 			compatible = "renesas,r9a09g047-ostm", "renesas,ostm";
 			reg = <0x0 0x11800000 0x0 0x1000>;
-- 
2.25.1
Re: [PATCH 0/5] soc: renesas: Add system controller support for RZ/G3E SoC
Posted by Geert Uytterhoeven 1 year ago 
Hi John,

On Fri, Dec 6, 2024 at 10:26 PM John Madieu
<john.madieu.xa@bp.renesas.com> wrote:
> This patch series adds support for the RZ/G3E system controller and extends
> the existing RZ/V2H(P) system controller to support syscon. The RZ/G3E
> system controller allows detecting various SoC features like core count,
> NPU availability, and CA55 PLL configuration.
>
> Key features:
> - Syscon support for both RZ/V2H and RZ/G3E system controllers
> - Detection of quad/dual core configuration
> - Detection of Ethos-U55 NPU presence
> - Validation of CA55 PLL frequency setting
> - SoC-specific extended identification through callbacks

Thanks for your series!

> This patch series depends upon [1] and [2].
>
> Tested:
> - Example of SoC detection:
> [    0.065608] renesas-rz-sysc 10430000.system-controller: Detected Renesas Quad Core RZ/G3E r9a09g047 Rev 0  with Ethos-U55
> - Example of PLL misconfiguration warning:
>  [    0.065616] renesas-rz-sysc 10430000.system-controller: CA55 PLL is not set to 1.7GHz
>
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=914097
> [2] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=912697

The latter points to an already-applied unrelated series.  I assume you
meant "[PATCH v2 00/15] Add initial USB support for the Renesas RZ/G3S
SoC"[3]?

[3] https://lore.kernel.org/all/20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com/


Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Re: [PATCH 0/5] soc: renesas: Add system controller support for RZ/G3E SoC
Posted by Rob Herring 1 year ago 
On Fri, Dec 06, 2024 at 10:25:54PM +0100, John Madieu wrote:
> This patch series adds support for the RZ/G3E system controller and extends
> the existing RZ/V2H(P) system controller to support syscon. The RZ/G3E
> system controller allows detecting various SoC features like core count,
> NPU availability, and CA55 PLL configuration.
> 
> Key features:
> - Syscon support for both RZ/V2H and RZ/G3E system controllers
> - Detection of quad/dual core configuration
> - Detection of Ethos-U55 NPU presence
> - Validation of CA55 PLL frequency setting
> - SoC-specific extended identification through callbacks

This series and some other questions about syscon prompted me to look 
into syscon driver a bit. Consider this resulting series[1] in context 
with your changes.

Rob

[1] https://lore.kernel.org/all/20241211-syscon-fixes-v1-3-b5ac8c219e96@kernel.org/
Re: [PATCH 0/5] soc: renesas: Add system controller support for RZ/G3E SoC
Posted by Geert Uytterhoeven 1 year ago 
Hi Rob,

On Wed, Dec 11, 2024 at 10:08 PM Rob Herring <robh@kernel.org> wrote:
> On Fri, Dec 06, 2024 at 10:25:54PM +0100, John Madieu wrote:
> > This patch series adds support for the RZ/G3E system controller and extends
> > the existing RZ/V2H(P) system controller to support syscon. The RZ/G3E
> > system controller allows detecting various SoC features like core count,
> > NPU availability, and CA55 PLL configuration.
> >
> > Key features:
> > - Syscon support for both RZ/V2H and RZ/G3E system controllers
> > - Detection of quad/dual core configuration
> > - Detection of Ethos-U55 NPU presence
> > - Validation of CA55 PLL frequency setting
> > - SoC-specific extended identification through callbacks
>
> This series and some other questions about syscon prompted me to look
> into syscon driver a bit. Consider this resulting series[1] in context
> with your changes.
>
> Rob
>
> [1] https://lore.kernel.org/all/20241211-syscon-fixes-v1-3-b5ac8c219e96@kernel.org/

Thank you, not having to add a "syscon" compatible value makes
perfect sense!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Patchew 2.1-devel-b67e4c2

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