Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
---
Documentation/arch/riscv/hwprobe.rst | 12 ++++++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 3 +++
arch/riscv/kernel/sys_hwprobe.c | 3 +++
3 files changed, 18 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 955fbcd19ce9..a9cb40e407a4 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -242,6 +242,18 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
defined in version 1.0 of the RISC-V Pointer Masking extensions.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
+ defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+ ("Added Chapter title to BF16").
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
+ defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+ ("Added Chapter title to BF16").
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
+ defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+ ("Added Chapter title to BF16").
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
mistakenly classified as a bitmask rather than a value.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 3af142b99f77..aecc1c800d54 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -73,6 +73,9 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
#define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
+#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 50)
+#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 51)
+#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 52)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index cb93adfffc48..bd215f58bd1b 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -131,6 +131,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZVE64D);
EXT_KEY(ZVE64F);
EXT_KEY(ZVE64X);
+ EXT_KEY(ZVFBFMIN);
+ EXT_KEY(ZVFBFWMA);
EXT_KEY(ZVFH);
EXT_KEY(ZVFHMIN);
EXT_KEY(ZVKB);
@@ -147,6 +149,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZCD);
EXT_KEY(ZCF);
EXT_KEY(ZFA);
+ EXT_KEY(ZFBFMIN);
EXT_KEY(ZFH);
EXT_KEY(ZFHMIN);
}
--
2.47.1
Possible conflict with:
https://lore.kernel.org/linux-riscv/20241111-v5_user_cfi_series-v8-22-dce14aa30207@rivosinc.com/
On 12/6/24 13:58, Inochi Amaoto wrote:
> Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Reviewed-by: Clément Léger <cleger@rivosinc.com>
> ---
> Documentation/arch/riscv/hwprobe.rst | 12 ++++++++++++
> arch/riscv/include/uapi/asm/hwprobe.h | 3 +++
> arch/riscv/kernel/sys_hwprobe.c | 3 +++
> 3 files changed, 18 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 955fbcd19ce9..a9cb40e407a4 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -242,6 +242,18 @@ The following keys are defined:
> * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
> defined in version 1.0 of the RISC-V Pointer Masking extensions.
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
> + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> + ("Added Chapter title to BF16").
> +
> + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
> + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> + ("Added Chapter title to BF16").
> +
> + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
> + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> + ("Added Chapter title to BF16").
> +
> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
> :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
> mistakenly classified as a bitmask rather than a value.
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 3af142b99f77..aecc1c800d54 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -73,6 +73,9 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
> #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
> #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
> +#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 50)
> +#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 51)
> +#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 52)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index cb93adfffc48..bd215f58bd1b 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -131,6 +131,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZVE64D);
> EXT_KEY(ZVE64F);
> EXT_KEY(ZVE64X);
> + EXT_KEY(ZVFBFMIN);
> + EXT_KEY(ZVFBFWMA);
> EXT_KEY(ZVFH);
> EXT_KEY(ZVFHMIN);
> EXT_KEY(ZVKB);
> @@ -147,6 +149,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZCD);
> EXT_KEY(ZCF);
> EXT_KEY(ZFA);
> + EXT_KEY(ZFBFMIN);
> EXT_KEY(ZFH);
> EXT_KEY(ZFHMIN);
> }
On Tue, Dec 17, 2024 at 12:00:23AM +0800, Yangyu Chen wrote:
> Possible conflict with: https://lore.kernel.org/linux-riscv/20241111-v5_user_cfi_series-v8-22-dce14aa30207@rivosinc.com/
>
Yeah, I know the conflict. As the time of merging these patch is
uncertain, what I can do now is to match the upstream code.
Regards,
Inochi
> On 12/6/24 13:58, Inochi Amaoto wrote:
> > Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > Reviewed-by: Clément Léger <cleger@rivosinc.com>
> > ---
> > Documentation/arch/riscv/hwprobe.rst | 12 ++++++++++++
> > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++
> > arch/riscv/kernel/sys_hwprobe.c | 3 +++
> > 3 files changed, 18 insertions(+)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index 955fbcd19ce9..a9cb40e407a4 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -242,6 +242,18 @@ The following keys are defined:
> > * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
> > defined in version 1.0 of the RISC-V Pointer Masking extensions.
> > + * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
> > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> > + ("Added Chapter title to BF16").
> > +
> > + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
> > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> > + ("Added Chapter title to BF16").
> > +
> > + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
> > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> > + ("Added Chapter title to BF16").
> > +
> > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
> > :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
> > mistakenly classified as a bitmask rather than a value.
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index 3af142b99f77..aecc1c800d54 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -73,6 +73,9 @@ struct riscv_hwprobe {
> > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
> > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
> > #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
> > +#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 50)
> > +#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 51)
> > +#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 52)
> > #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index cb93adfffc48..bd215f58bd1b 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -131,6 +131,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> > EXT_KEY(ZVE64D);
> > EXT_KEY(ZVE64F);
> > EXT_KEY(ZVE64X);
> > + EXT_KEY(ZVFBFMIN);
> > + EXT_KEY(ZVFBFWMA);
> > EXT_KEY(ZVFH);
> > EXT_KEY(ZVFHMIN);
> > EXT_KEY(ZVKB);
> > @@ -147,6 +149,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> > EXT_KEY(ZCD);
> > EXT_KEY(ZCF);
> > EXT_KEY(ZFA);
> > + EXT_KEY(ZFBFMIN);
> > EXT_KEY(ZFH);
> > EXT_KEY(ZFHMIN);
> > }
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Tue, Dec 17, 2024 at 08:40:37AM +0800, Inochi Amaoto wrote: > On Tue, Dec 17, 2024 at 12:00:23AM +0800, Yangyu Chen wrote: > > Possible conflict with: https://lore.kernel.org/linux-riscv/20241111-v5_user_cfi_series-v8-22-dce14aa30207@rivosinc.com/ > > > > Yeah, I know the conflict. As the time of merging these patch is > uncertain, what I can do now is to match the upstream code. The solution is to not worry about it. Palmer can resolve trivial numerical conflicts like this.
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