The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to
build Energy Model which in turn is used by EAS to take placement
decisions. So add it to QCS8300 SoC.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 73abf2ef9c9f..2996b09e4c54 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -44,6 +44,8 @@ cpu0: cpu@0 {
 			next-level-cache = <&l2_0>;
 			power-domains = <&cpu_pd0>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <472>;
 
 			l2_0: l2-cache {
 				compatible = "cache";
@@ -61,6 +63,8 @@ cpu1: cpu@100 {
 			next-level-cache = <&l2_1>;
 			power-domains = <&cpu_pd1>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <472>;
 
 			l2_1: l2-cache {
 				compatible = "cache";
@@ -78,6 +82,8 @@ cpu2: cpu@200 {
 			next-level-cache = <&l2_2>;
 			power-domains = <&cpu_pd2>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <507>;
 
 			l2_2: l2-cache {
 				compatible = "cache";
@@ -95,6 +101,8 @@ cpu3: cpu@300 {
 			next-level-cache = <&l2_3>;
 			power-domains = <&cpu_pd3>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <507>;
 
 			l2_3: l2-cache {
 				compatible = "cache";
@@ -112,6 +120,8 @@ cpu4: cpu@10000 {
 			next-level-cache = <&l2_4>;
 			power-domains = <&cpu_pd4>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 
 			l2_4: l2-cache {
 				compatible = "cache";
@@ -129,6 +139,8 @@ cpu5: cpu@10100 {
 			next-level-cache = <&l2_5>;
 			power-domains = <&cpu_pd5>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 
 			l2_5: l2-cache {
 				compatible = "cache";
@@ -146,6 +158,8 @@ cpu6: cpu@10200 {
 			next-level-cache = <&l2_6>;
 			power-domains = <&cpu_pd6>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 
 			l2_6: l2-cache {
 				compatible = "cache";
@@ -163,6 +177,8 @@ cpu7: cpu@10300 {
 			next-level-cache = <&l2_7>;
 			power-domains = <&cpu_pd7>;
 			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
 
 			l2_7: l2-cache {
 				compatible = "cache";

---
base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7
change-id: 20241206-qcs8300_dpc-230f7767f603

Best regards,
-- 
Jingyi Wang <quic_jingyw@quicinc.com>

On Fri, 06 Dec 2024 14:41:13 +0800, Jingyi Wang wrote:
> The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to
> build Energy Model which in turn is used by EAS to take placement
> decisions. So add it to QCS8300 SoC.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: qcs8300: Add capacity and DPC properties
      commit: ce4b3c48e4725a28b4e52802fdfb963f176801bc

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

On 6.12.2024 7:41 AM, Jingyi Wang wrote:
> The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to
> build Energy Model which in turn is used by EAS to take placement
> decisions. So add it to QCS8300 SoC.
> 
> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> ---

I'm willing to believe these numbers for a78c vs a55

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad