Add PWM driver support for Andes atcpit100.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
MAINTAINERS | 1 +
drivers/pwm/Kconfig | 17 +++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-atcpit100.c | 289 ++++++++++++++++++++++++++++++++++++
4 files changed, 308 insertions(+)
create mode 100644 drivers/pwm/pwm-atcpit100.c
diff --git a/MAINTAINERS b/MAINTAINERS
index ebbc7edcf077..39c6e1f21339 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3555,6 +3555,7 @@ ATCPIT100 PWM DRIVER
M: Ben Zong-You Xie <ben717@andestech.com>
S: Supported
F: Documentation/devicetree/bindings/pwm/andestech,atcpit100-pwm.yaml
+F: drivers/pwm/pwm-atcpit100.c
ATHEROS 71XX/9XXX GPIO DRIVER
M: Alban Bedel <albeu@free.fr>
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 0915c1e7df16..f45ff74fb44e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -66,6 +66,23 @@ config PWM_APPLE
To compile this driver as a module, choose M here: the module
will be called pwm-apple.
+config PWM_ATCPIT100
+ tristate "Andes ATCPIT100 PWM support"
+ depends on OF && HAS_IOMEM
+ depends on RISCV || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ Generic PWM framework driver for ATCPIT100 on Andes AE350 platform
+
+ The ATCPIT100 Programmable Interval Timer (PIT) is a set of compact
+ multi-function timers, which can be used as pulse width
+ modulators (PWM) as well as simple timers. ATCPIT100 supports up to 4
+ PIT channels. Each PIT channel can be a simple timer or PWM, or a
+ combination of timer and PWM.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-atcpit100.
+
config PWM_ATMEL
tristate "Atmel PWM support"
depends on ARCH_AT91 || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 9081e0c0e9e0..ad6e803f12d0 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
obj-$(CONFIG_PWM_ADP5585) += pwm-adp5585.o
obj-$(CONFIG_PWM_APPLE) += pwm-apple.o
+obj-$(CONFIG_PWM_ATCPIT100) += pwm-atcpit100.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
diff --git a/drivers/pwm/pwm-atcpit100.c b/drivers/pwm/pwm-atcpit100.c
new file mode 100644
index 000000000000..a8bbac878130
--- /dev/null
+++ b/drivers/pwm/pwm-atcpit100.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * PWM driver for ATCPIT100 on Andes AE350 platform
+ *
+ * Copyright (C) 2024 Andes Technology Corporation.
+ *
+ * Limitations:
+ * - When disabling a channel, the current period will not be completed, and the
+ * output will be constant zero.
+ * - The current period will be completed first while reconfiguring.
+ * - Further, if the reconfiguration changes the clock source, the output will
+ * not be the old one nor the new one. And the output will be the new one
+ * once writing to the reload register.
+ * - The hardware can neither do a 0% nor a 100% relative duty cycle.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+#include <linux/time.h>
+#include <linux/types.h>
+
+#define ATCPIT100_CHANNEL_MAX 4
+#define ATCPIT100_CHANNEL_ENABLE 0x1C
+#define ATCPIT100_CHANNEL_ENABLE_PWM(ch) BIT(3 + (4 * ch))
+#define ATCPIT100_CHANNEL_CTRL(ch) (0x20 + (0x10 * ch))
+#define ATCPIT100_CHANNEL_CTRL_MODE_PWM 0x04
+#define ATCPIT100_CHANNEL_CTRL_CLK BIT(3)
+#define ATCPIT100_CHANNEL_CTRL_MASK GENMASK(4, 0)
+#define ATCPIT100_CHANNEL_RELOAD(ch) (0x24 + (0x10 * ch))
+#define ATCPIT100_CHANNEL_RELOAD_HIGH GENMASK(31, 16)
+#define ATCPIT100_CHANNEL_RELOAD_LOW GENMASK(15, 0)
+#define ATCPIT100_CYCLE_MIN 1
+#define ATCPIT100_CYCLE_MAX 0x010000
+#define ATCPIT100_IS_VALID_PERIOD(p) \
+ in_range(p, min_period, max_period - min_period + 1)
+
+enum atcpit100_clk {
+ ATCPIT100_CLK_EXT = 0,
+ ATCPIT100_CLK_APB,
+ NUM_ATCPIT100_CLK
+};
+
+struct atcpit100_pwm {
+ struct regmap *regmap;
+ struct clk *ext_clk;
+ struct clk *apb_clk;
+};
+
+static const struct regmap_config atcpit100_pwm_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+};
+
+static inline struct atcpit100_pwm *to_atcpit100_pwm(struct pwm_chip *chip)
+{
+ return pwmchip_get_drvdata(chip);
+}
+
+static int atcpit100_pwm_enable(struct pwm_chip *chip, unsigned int channel,
+ bool enable)
+{
+ unsigned int enable_bit = ATCPIT100_CHANNEL_ENABLE_PWM(channel);
+ struct atcpit100_pwm *ap = to_atcpit100_pwm(chip);
+
+ return regmap_update_bits(ap->regmap, ATCPIT100_CHANNEL_ENABLE,
+ enable_bit, enable ? enable_bit : 0);
+}
+
+static int atcpit100_pwm_config(struct pwm_chip *chip, unsigned int channel,
+ const struct pwm_state *state)
+{
+ int clk;
+ int ret;
+ unsigned int reload_val;
+ unsigned long rate[NUM_ATCPIT100_CLK];
+ u64 max_period;
+ u64 min_period;
+ u64 high_cycle;
+ u64 low_cycle;
+ struct atcpit100_pwm *ap = to_atcpit100_pwm(chip);
+ unsigned int ctrl_val = ATCPIT100_CHANNEL_CTRL_MODE_PWM;
+ u64 high_period = state->duty_cycle;
+ u64 low_period = state->period - high_period;
+
+ rate[ATCPIT100_CLK_EXT] = clk_get_rate(ap->ext_clk);
+ rate[ATCPIT100_CLK_APB] = clk_get_rate(ap->apb_clk);
+
+ /*
+ * Reload register for PWM mode:
+ *
+ * 31 : 16 15 : 0
+ * PWM16_Hi | PWM16_Lo
+ *
+ * In the PWM mode, the high period is (PWM16_Hi + 1) cycles, and the
+ * low period is (PWM16_Lo + 1) cycles. Since we need to write
+ * "numcycles - 1" to the register, the valid range of numcycles will
+ * be between 1 to 0x10000. Calculate the possible periods that satisfy
+ * the above restriction:
+ *
+ * Let m = 1, M = 0x10000,
+ * m <= floor(cycle) <= M
+ * <=> m <= floor(rate * period / NSEC_PER_SEC) <= M
+ * <=> m <= rate * period / NSEC_PER_SEC < M + 1
+ * <=> m * NSEC_PER_SEC / rate <= period < (M + 1) * NSEC_PER_SEC / rate
+ * <=> ceil(m * NSEC_PER_SEC / rate) <= period <= ceil((M + 1) * NSEC_PER_SEC / rate) - 1
+ *
+ * Since there are two clock sources for ATCPIT100, if the period is not
+ * valid for the first clock source, then the second clock source will
+ * be checked. Reject the request when both clock sources are not valid
+ * for the settings.
+ */
+ for (clk = ATCPIT100_CLK_EXT; clk < NUM_ATCPIT100_CLK; clk++) {
+ max_period =
+ DIV64_U64_ROUND_UP(
+ (ATCPIT100_CYCLE_MAX + 1) * NSEC_PER_SEC,
+ rate[clk]) - 1;
+ min_period =
+ DIV64_U64_ROUND_UP(ATCPIT100_CYCLE_MIN * NSEC_PER_SEC,
+ rate[clk]);
+
+ if (ATCPIT100_IS_VALID_PERIOD(high_period) &&
+ ATCPIT100_IS_VALID_PERIOD(low_period))
+ break;
+ }
+
+ if (clk == NUM_ATCPIT100_CLK)
+ return -EINVAL;
+
+ /*
+ * Once changing the clock source here, the output will be neither the
+ * old one nor the new one until writing to the reload register.
+ */
+ ctrl_val |= clk ? ATCPIT100_CHANNEL_CTRL_CLK : 0;
+ ret = regmap_update_bits(ap->regmap, ATCPIT100_CHANNEL_CTRL(channel),
+ ATCPIT100_CHANNEL_CTRL_MASK, ctrl_val);
+ if (ret)
+ return ret;
+
+ high_cycle = mul_u64_u64_div_u64(rate[clk], high_period, NSEC_PER_SEC);
+ low_cycle = mul_u64_u64_div_u64(rate[clk], low_period, NSEC_PER_SEC);
+ reload_val = FIELD_PREP(ATCPIT100_CHANNEL_RELOAD_HIGH, high_cycle - 1) |
+ FIELD_PREP(ATCPIT100_CHANNEL_RELOAD_LOW, low_cycle - 1);
+
+ return regmap_write(ap->regmap, ATCPIT100_CHANNEL_RELOAD(channel),
+ reload_val);
+}
+
+static int atcpit100_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ int ret;
+ unsigned int channel = pwm->hwpwm;
+
+ /* ATCPIT100 PWM driver now only supports normal polarity. */
+ if (state->polarity != PWM_POLARITY_NORMAL)
+ return -EINVAL;
+
+ if (!state->enabled) {
+ if (pwm->state.enabled)
+ return atcpit100_pwm_enable(chip, channel, false);
+
+ return 0;
+ }
+
+ if (ret)
+ return ret;
+
+ ret = atcpit100_pwm_config(chip, channel, state);
+ if (ret)
+ return ret;
+
+ return atcpit100_pwm_enable(chip, channel, true);
+}
+
+static int atcpit100_pwm_get_state(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ int ret;
+ unsigned int ctrl_val;
+ unsigned int reload_val;
+ unsigned long rate;
+ u16 pwm_high;
+ u16 pwm_low;
+ unsigned int channel = pwm->hwpwm;
+ struct atcpit100_pwm *ap = to_atcpit100_pwm(chip);
+
+ ret = regmap_read(ap->regmap, ATCPIT100_CHANNEL_CTRL(channel),
+ &ctrl_val);
+ if (ret)
+ return ret;
+
+ rate = (ctrl_val & ATCPIT100_CHANNEL_CTRL_CLK) ?
+ clk_get_rate(ap->apb_clk) : clk_get_rate(ap->ext_clk);
+ state->enabled =
+ regmap_test_bits(ap->regmap, ATCPIT100_CHANNEL_ENABLE,
+ ATCPIT100_CHANNEL_ENABLE_PWM(channel));
+ state->polarity = PWM_POLARITY_NORMAL;
+ ret = regmap_read(ap->regmap, ATCPIT100_CHANNEL_RELOAD(channel),
+ &reload_val);
+ if (ret)
+ return ret;
+
+ pwm_high = FIELD_GET(ATCPIT100_CHANNEL_RELOAD_HIGH, reload_val);
+ pwm_low = FIELD_GET(ATCPIT100_CHANNEL_RELOAD_LOW, reload_val);
+ state->duty_cycle =
+ DIV64_U64_ROUND_UP((pwm_high + 1) * NSEC_PER_SEC, rate);
+ state->period =
+ state->duty_cycle +
+ DIV64_U64_ROUND_UP((pwm_low + 1) * NSEC_PER_SEC, rate);
+
+ return 0;
+}
+
+static const struct pwm_ops atcpit_pwm_ops = {
+ .apply = atcpit100_pwm_apply,
+ .get_state = atcpit100_pwm_get_state,
+};
+
+static int atcpit100_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct atcpit100_pwm *ap;
+ struct pwm_chip *chip;
+ void __iomem *base;
+ int ret;
+
+ chip = devm_pwmchip_alloc(dev, ATCPIT100_CHANNEL_MAX, sizeof(*ap));
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+
+ ap = to_atcpit100_pwm(chip);
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ ap->ext_clk = devm_clk_get(dev, "ext");
+ if (IS_ERR(ap->ext_clk)) {
+ dev_err_probe(dev, PTR_ERR(ap->ext_clk),
+ "failed to obtain external clock\n");
+ }
+
+ ap->apb_clk = devm_clk_get_enabled(dev, "apb");
+ if (IS_ERR(ap->apb_clk)) {
+ dev_err_probe(dev, PTR_ERR(ap->apb_clk),
+ "failed to obtain APB clock\n");
+ }
+
+ ap->regmap = devm_regmap_init_mmio(dev, base,
+ &atcpit100_pwm_regmap_config);
+ if (IS_ERR(ap->regmap)) {
+ return dev_err_probe(dev, PTR_ERR(ap->regmap),
+ "failed to init register map\n");
+ }
+
+ chip->ops = &atcpit_pwm_ops;
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add PWM chip\n");
+
+ return 0;
+}
+
+static const struct of_device_id atcpit100_pwm_dt[] = {
+ { .compatible = "andestech,atcpit100-pwm" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, atcpit100_pwm_dt);
+
+static struct platform_driver atcpit100_pwm_driver = {
+ .driver = {
+ .name = "atcpit100-pwm",
+ .of_match_table = atcpit100_pwm_dt,
+ },
+ .probe = atcpit100_pwm_probe,
+};
+module_platform_driver(atcpit100_pwm_driver);
+
+MODULE_AUTHOR("Ben Zong-You Xie <ben717@andestech.com>");
+MODULE_DESCRIPTION("Andes ATCPIT100 PWM driver");
+MODULE_LICENSE("GPL");
--
2.34.1Hi Ben,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master thierry-reding-pwm/for-next v6.13-rc1 next-20241128]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Ben-Zong-You-Xie/dt-bindings-pwm-add-atcpit100-pwm/20241202-140437
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20241202060147.1271264-3-ben717%40andestech.com
patch subject: [PATCH v2 2/2] pwm: atcpit100: add Andes PWM driver support
config: hexagon-allyesconfig (https://download.01.org/0day-ci/archive/20241202/202412022109.FiMppwWS-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project 592c0fe55f6d9a811028b5f3507be91458ab2713)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241202/202412022109.FiMppwWS-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202412022109.FiMppwWS-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/pwm/pwm-atcpit100.c:25:
In file included from include/linux/regmap.h:20:
In file included from include/linux/iopoll.h:14:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:548:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
548 | val = __raw_readb(PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:561:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
561 | val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
| ~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu'
37 | #define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
| ^
In file included from drivers/pwm/pwm-atcpit100.c:25:
In file included from include/linux/regmap.h:20:
In file included from include/linux/iopoll.h:14:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:574:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
574 | val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
| ~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu'
35 | #define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
| ^
In file included from drivers/pwm/pwm-atcpit100.c:25:
In file included from include/linux/regmap.h:20:
In file included from include/linux/iopoll.h:14:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:585:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
585 | __raw_writeb(value, PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:595:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
595 | __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:605:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
605 | __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
>> drivers/pwm/pwm-atcpit100.c:123:31: warning: overflow in expression; result is 94'030'336 with type 'long' [-Winteger-overflow]
122 | DIV64_U64_ROUND_UP(
| ~~~~~~~~~~~~~~~~~~~
123 | (ATCPIT100_CYCLE_MAX + 1) * NSEC_PER_SEC,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
124 | rate[clk]) - 1;
| ~~~~~~~~~~
include/linux/math64.h:298:32: note: expanded from macro 'DIV64_U64_ROUND_UP'
298 | ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); })
| ^~
>> drivers/pwm/pwm-atcpit100.c:173:6: warning: variable 'ret' is uninitialized when used here [-Wuninitialized]
173 | if (ret)
| ^~~
drivers/pwm/pwm-atcpit100.c:159:9: note: initialize the variable 'ret' to silence this warning
159 | int ret;
| ^
| = 0
8 warnings generated.
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for MODVERSIONS
Depends on [n]: MODULES [=y] && !COMPILE_TEST [=y]
Selected by [y]:
- RANDSTRUCT_FULL [=y] && (CC_HAS_RANDSTRUCT [=y] || GCC_PLUGINS [=n]) && MODULES [=y]
WARNING: unmet direct dependencies detected for GET_FREE_REGION
Depends on [n]: SPARSEMEM [=n]
Selected by [y]:
- RESOURCE_KUNIT_TEST [=y] && RUNTIME_TESTING_MENU [=y] && KUNIT [=y]
vim +123 drivers/pwm/pwm-atcpit100.c
76
77 static int atcpit100_pwm_config(struct pwm_chip *chip, unsigned int channel,
78 const struct pwm_state *state)
79 {
80 int clk;
81 int ret;
82 unsigned int reload_val;
83 unsigned long rate[NUM_ATCPIT100_CLK];
84 u64 max_period;
85 u64 min_period;
86 u64 high_cycle;
87 u64 low_cycle;
88 struct atcpit100_pwm *ap = to_atcpit100_pwm(chip);
89 unsigned int ctrl_val = ATCPIT100_CHANNEL_CTRL_MODE_PWM;
90 u64 high_period = state->duty_cycle;
91 u64 low_period = state->period - high_period;
92
93 rate[ATCPIT100_CLK_EXT] = clk_get_rate(ap->ext_clk);
94 rate[ATCPIT100_CLK_APB] = clk_get_rate(ap->apb_clk);
95
96 /*
97 * Reload register for PWM mode:
98 *
99 * 31 : 16 15 : 0
100 * PWM16_Hi | PWM16_Lo
101 *
102 * In the PWM mode, the high period is (PWM16_Hi + 1) cycles, and the
103 * low period is (PWM16_Lo + 1) cycles. Since we need to write
104 * "numcycles - 1" to the register, the valid range of numcycles will
105 * be between 1 to 0x10000. Calculate the possible periods that satisfy
106 * the above restriction:
107 *
108 * Let m = 1, M = 0x10000,
109 * m <= floor(cycle) <= M
110 * <=> m <= floor(rate * period / NSEC_PER_SEC) <= M
111 * <=> m <= rate * period / NSEC_PER_SEC < M + 1
112 * <=> m * NSEC_PER_SEC / rate <= period < (M + 1) * NSEC_PER_SEC / rate
113 * <=> ceil(m * NSEC_PER_SEC / rate) <= period <= ceil((M + 1) * NSEC_PER_SEC / rate) - 1
114 *
115 * Since there are two clock sources for ATCPIT100, if the period is not
116 * valid for the first clock source, then the second clock source will
117 * be checked. Reject the request when both clock sources are not valid
118 * for the settings.
119 */
120 for (clk = ATCPIT100_CLK_EXT; clk < NUM_ATCPIT100_CLK; clk++) {
121 max_period =
122 DIV64_U64_ROUND_UP(
> 123 (ATCPIT100_CYCLE_MAX + 1) * NSEC_PER_SEC,
124 rate[clk]) - 1;
125 min_period =
126 DIV64_U64_ROUND_UP(ATCPIT100_CYCLE_MIN * NSEC_PER_SEC,
127 rate[clk]);
128
129 if (ATCPIT100_IS_VALID_PERIOD(high_period) &&
130 ATCPIT100_IS_VALID_PERIOD(low_period))
131 break;
132 }
133
134 if (clk == NUM_ATCPIT100_CLK)
135 return -EINVAL;
136
137 /*
138 * Once changing the clock source here, the output will be neither the
139 * old one nor the new one until writing to the reload register.
140 */
141 ctrl_val |= clk ? ATCPIT100_CHANNEL_CTRL_CLK : 0;
142 ret = regmap_update_bits(ap->regmap, ATCPIT100_CHANNEL_CTRL(channel),
143 ATCPIT100_CHANNEL_CTRL_MASK, ctrl_val);
144 if (ret)
145 return ret;
146
147 high_cycle = mul_u64_u64_div_u64(rate[clk], high_period, NSEC_PER_SEC);
148 low_cycle = mul_u64_u64_div_u64(rate[clk], low_period, NSEC_PER_SEC);
149 reload_val = FIELD_PREP(ATCPIT100_CHANNEL_RELOAD_HIGH, high_cycle - 1) |
150 FIELD_PREP(ATCPIT100_CHANNEL_RELOAD_LOW, low_cycle - 1);
151
152 return regmap_write(ap->regmap, ATCPIT100_CHANNEL_RELOAD(channel),
153 reload_val);
154 }
155
156 static int atcpit100_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
157 const struct pwm_state *state)
158 {
159 int ret;
160 unsigned int channel = pwm->hwpwm;
161
162 /* ATCPIT100 PWM driver now only supports normal polarity. */
163 if (state->polarity != PWM_POLARITY_NORMAL)
164 return -EINVAL;
165
166 if (!state->enabled) {
167 if (pwm->state.enabled)
168 return atcpit100_pwm_enable(chip, channel, false);
169
170 return 0;
171 }
172
> 173 if (ret)
174 return ret;
175
176 ret = atcpit100_pwm_config(chip, channel, state);
177 if (ret)
178 return ret;
179
180 return atcpit100_pwm_enable(chip, channel, true);
181 }
182
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Ben,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master thierry-reding-pwm/for-next v6.13-rc1 next-20241128]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Ben-Zong-You-Xie/dt-bindings-pwm-add-atcpit100-pwm/20241202-140437
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20241202060147.1271264-3-ben717%40andestech.com
patch subject: [PATCH v2 2/2] pwm: atcpit100: add Andes PWM driver support
config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20241202/202412021900.oCRrT3PV-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241202/202412021900.oCRrT3PV-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202412021900.oCRrT3PV-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/jiffies.h:7,
from include/linux/ktime.h:25,
from include/linux/timer.h:6,
from include/linux/workqueue.h:9,
from include/linux/srcu.h:21,
from include/linux/notifier.h:16,
from include/linux/clk.h:14,
from drivers/pwm/pwm-atcpit100.c:18:
drivers/pwm/pwm-atcpit100.c: In function 'atcpit100_pwm_config':
>> drivers/pwm/pwm-atcpit100.c:123:59: warning: integer overflow in expression of type 'long int' results in '94030336' [-Woverflow]
123 | (ATCPIT100_CYCLE_MAX + 1) * NSEC_PER_SEC,
| ^
include/linux/math64.h:298:39: note: in definition of macro 'DIV64_U64_ROUND_UP'
298 | ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); })
| ^~
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for GET_FREE_REGION
Depends on [n]: SPARSEMEM [=n]
Selected by [y]:
- RESOURCE_KUNIT_TEST [=y] && RUNTIME_TESTING_MENU [=y] && KUNIT [=y]
vim +123 drivers/pwm/pwm-atcpit100.c
76
77 static int atcpit100_pwm_config(struct pwm_chip *chip, unsigned int channel,
78 const struct pwm_state *state)
79 {
80 int clk;
81 int ret;
82 unsigned int reload_val;
83 unsigned long rate[NUM_ATCPIT100_CLK];
84 u64 max_period;
85 u64 min_period;
86 u64 high_cycle;
87 u64 low_cycle;
88 struct atcpit100_pwm *ap = to_atcpit100_pwm(chip);
89 unsigned int ctrl_val = ATCPIT100_CHANNEL_CTRL_MODE_PWM;
90 u64 high_period = state->duty_cycle;
91 u64 low_period = state->period - high_period;
92
93 rate[ATCPIT100_CLK_EXT] = clk_get_rate(ap->ext_clk);
94 rate[ATCPIT100_CLK_APB] = clk_get_rate(ap->apb_clk);
95
96 /*
97 * Reload register for PWM mode:
98 *
99 * 31 : 16 15 : 0
100 * PWM16_Hi | PWM16_Lo
101 *
102 * In the PWM mode, the high period is (PWM16_Hi + 1) cycles, and the
103 * low period is (PWM16_Lo + 1) cycles. Since we need to write
104 * "numcycles - 1" to the register, the valid range of numcycles will
105 * be between 1 to 0x10000. Calculate the possible periods that satisfy
106 * the above restriction:
107 *
108 * Let m = 1, M = 0x10000,
109 * m <= floor(cycle) <= M
110 * <=> m <= floor(rate * period / NSEC_PER_SEC) <= M
111 * <=> m <= rate * period / NSEC_PER_SEC < M + 1
112 * <=> m * NSEC_PER_SEC / rate <= period < (M + 1) * NSEC_PER_SEC / rate
113 * <=> ceil(m * NSEC_PER_SEC / rate) <= period <= ceil((M + 1) * NSEC_PER_SEC / rate) - 1
114 *
115 * Since there are two clock sources for ATCPIT100, if the period is not
116 * valid for the first clock source, then the second clock source will
117 * be checked. Reject the request when both clock sources are not valid
118 * for the settings.
119 */
120 for (clk = ATCPIT100_CLK_EXT; clk < NUM_ATCPIT100_CLK; clk++) {
121 max_period =
122 DIV64_U64_ROUND_UP(
> 123 (ATCPIT100_CYCLE_MAX + 1) * NSEC_PER_SEC,
124 rate[clk]) - 1;
125 min_period =
126 DIV64_U64_ROUND_UP(ATCPIT100_CYCLE_MIN * NSEC_PER_SEC,
127 rate[clk]);
128
129 if (ATCPIT100_IS_VALID_PERIOD(high_period) &&
130 ATCPIT100_IS_VALID_PERIOD(low_period))
131 break;
132 }
133
134 if (clk == NUM_ATCPIT100_CLK)
135 return -EINVAL;
136
137 /*
138 * Once changing the clock source here, the output will be neither the
139 * old one nor the new one until writing to the reload register.
140 */
141 ctrl_val |= clk ? ATCPIT100_CHANNEL_CTRL_CLK : 0;
142 ret = regmap_update_bits(ap->regmap, ATCPIT100_CHANNEL_CTRL(channel),
143 ATCPIT100_CHANNEL_CTRL_MASK, ctrl_val);
144 if (ret)
145 return ret;
146
147 high_cycle = mul_u64_u64_div_u64(rate[clk], high_period, NSEC_PER_SEC);
148 low_cycle = mul_u64_u64_div_u64(rate[clk], low_period, NSEC_PER_SEC);
149 reload_val = FIELD_PREP(ATCPIT100_CHANNEL_RELOAD_HIGH, high_cycle - 1) |
150 FIELD_PREP(ATCPIT100_CHANNEL_RELOAD_LOW, low_cycle - 1);
151
152 return regmap_write(ap->regmap, ATCPIT100_CHANNEL_RELOAD(channel),
153 reload_val);
154 }
155
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