The Allwinner A100 has a system configuration block, denoted as SYS_CFG
in the user manual's memory map. It is undocumented in the manual, but
a glance at the vendor tree shows this block is similar to its
predecessors in the A64 and H6. The A100 also has 3 SRAM blocks: A1, A2,
and C. Add all of these to the SoC's device tree.
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 31 ++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 29ac7716c7a5284ccf8af675db9c7d016785f0ff..31540a7ca1f01c6c2e69e329054aca16ffd112c4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -101,6 +101,37 @@ soc {
#size-cells = <1>;
ranges = <0 0 0 0x3fffffff>;
+ syscon: syscon@3000000 {
+ compatible = "allwinner,sun50i-a100-system-control",
+ "allwinner,sun50i-a64-system-control";
+ reg = <0x03000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_a1: sram@20000 {
+ compatible = "mmio-sram";
+ reg = <0x00020000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00020000 0x4000>;
+ };
+ sram_c: sram@24000 {
+ compatible = "mmio-sram";
+ reg = <0x024000 0x21000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x024000 0x21000>;
+ };
+ sram_a2: sram@100000 {
+ compatible = "mmio-sram";
+ reg = <0x0100000 0x14000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0100000 0x14000>;
+ };
+ };
+
ccu: clock@3001000 {
compatible = "allwinner,sun50i-a100-ccu";
reg = <0x03001000 0x1000>;
--
2.47.1
On Mon, Dec 2, 2024 at 12:43 PM Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>
> The Allwinner A100 has a system configuration block, denoted as SYS_CFG
> in the user manual's memory map. It is undocumented in the manual, but
> a glance at the vendor tree shows this block is similar to its
> predecessors in the A64 and H6. The A100 also has 3 SRAM blocks: A1, A2,
> and C. Add all of these to the SoC's device tree.
>
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 31 ++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index 29ac7716c7a5284ccf8af675db9c7d016785f0ff..31540a7ca1f01c6c2e69e329054aca16ffd112c4 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -101,6 +101,37 @@ soc {
> #size-cells = <1>;
> ranges = <0 0 0 0x3fffffff>;
>
> + syscon: syscon@3000000 {
> + compatible = "allwinner,sun50i-a100-system-control",
> + "allwinner,sun50i-a64-system-control";
> + reg = <0x03000000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram_a1: sram@20000 {
> + compatible = "mmio-sram";
> + reg = <0x00020000 0x4000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x00020000 0x4000>;
> + };
Each child node should have an empty line preceding it, as mentioned
in the dts coding style doc:
Documentation/devicetree/bindings/dts-coding-style.rst
ChenYu
> + sram_c: sram@24000 {
> + compatible = "mmio-sram";
> + reg = <0x024000 0x21000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x024000 0x21000>;
> + };
> + sram_a2: sram@100000 {
> + compatible = "mmio-sram";
> + reg = <0x0100000 0x14000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0100000 0x14000>;
> + };
> + };
> +
> ccu: clock@3001000 {
> compatible = "allwinner,sun50i-a100-ccu";
> reg = <0x03001000 0x1000>;
>
> --
> 2.47.1
>
On 12/2/24 10:13 AM, Cody Eksal wrote:
> The Allwinner A100 has a system configuration block, denoted as SYS_CFG
> in the user manual's memory map. It is undocumented in the manual, but
> a glance at the vendor tree shows this block is similar to its
> predecessors in the A64 and H6. The A100 also has 3 SRAM blocks: A1, A2,
> and C. Add all of these to the SoC's device tree.
>
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Reviewed-by: Parthiban Nallathambi <parthiban@linumiz.com>
Thanks,
Parthiban
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 31 ++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index 29ac7716c7a5284ccf8af675db9c7d016785f0ff..31540a7ca1f01c6c2e69e329054aca16ffd112c4 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -101,6 +101,37 @@ soc {
> #size-cells = <1>;
> ranges = <0 0 0 0x3fffffff>;
>
> + syscon: syscon@3000000 {
> + compatible = "allwinner,sun50i-a100-system-control",
> + "allwinner,sun50i-a64-system-control";
> + reg = <0x03000000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram_a1: sram@20000 {
> + compatible = "mmio-sram";
> + reg = <0x00020000 0x4000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x00020000 0x4000>;
> + };
> + sram_c: sram@24000 {
> + compatible = "mmio-sram";
> + reg = <0x024000 0x21000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x024000 0x21000>;
> + };
> + sram_a2: sram@100000 {
> + compatible = "mmio-sram";
> + reg = <0x0100000 0x14000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0100000 0x14000>;
> + };
> + };
> +
> ccu: clock@3001000 {
> compatible = "allwinner,sun50i-a100-ccu";
> reg = <0x03001000 0x1000>;
>
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