Add device tree bindings for AMD Versal NET EDAC for DDR controller.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
---
.../amd,versalnet-edac.yaml | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml
new file mode 100644
index 000000000000..22a4669c46b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/amd,versalnet-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD Versal NET EDAC
+
+maintainers:
+ - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
+
+description:
+ The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
+ 4X memory interfaces. Versal NET DDR memory controller has an optional ECC support
+ which correct single bit ECC errors and detect double bit ECC errors.
+ It also has support for reporting other errors like MMCM (Mixed-Mode Clock
+ Manager) errors and General software errors.
+
+properties:
+ compatible:
+ const: amd,versalnet-edac
+
+ amd,dwidth:
+ description:
+ DDR memory controller device width.
+ enum: [16, 32]
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ amd,num-chans:
+ description:
+ Number of channels.
+ enum: [1, 2]
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ amd,num-rank:
+ description:
+ Number of rank.
+ enum: [1, 2, 4]
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - amd,dwidth
+ - amd,num-chans
+ - amd,num-rank
+
+additionalProperties: false
+
+examples:
+ - |
+ memory-controller {
+ compatible = "amd,versalnet-edac";
+ amd,dwidth = <32>;
+ amd,num-chans = <2>;
+ amd,num-rank = <1>;
+ };
--
2.17.1On Fri, Nov 22, 2024 at 03:36:23PM +0530, Shubhrajyoti Datta wrote: > Add device tree bindings for AMD Versal NET EDAC for DDR controller. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > --- > Use tools to create cc-list, like b4 or: https://github.com/krzk/tools/blob/master/linux/.bash_aliases_linux#L92 so you won't make a typo in my email. > .../amd,versalnet-edac.yaml | 56 +++++++++++++++++++ > 1 file changed, 56 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml > > diff --git a/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml > new file mode 100644 > index 000000000000..22a4669c46b6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml > @@ -0,0 +1,56 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/amd,versalnet-edac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: AMD Versal NET EDAC s/EDAC/Memory Controller or something similar, I guess. > + > +maintainers: > + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > + > +description: > + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ > + 4X memory interfaces. Versal NET DDR memory controller has an optional ECC support > + which correct single bit ECC errors and detect double bit ECC errors. > + It also has support for reporting other errors like MMCM (Mixed-Mode Clock > + Manager) errors and General software errors. > + > +properties: > + compatible: > + const: amd,versalnet-edac Why using different name than all others? Keep consistent stuff for your SoCs. Also, s/edac/memory-controller/, depending what this stuff really is. > + > + amd,dwidth: > + description: > + DDR memory controller device width. Use existing properties. > + enum: [16, 32] > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + amd,num-chans: > + description: > + Number of channels. Use existing properties, e.g. some of the DDR schemas describing memory. Look how other bindings describe actual chips. > + enum: [1, 2] > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + amd,num-rank: > + description: > + Number of rank. > + enum: [1, 2, 4] > + $ref: /schemas/types.yaml#/definitions/uint32 > + > +required: > + - compatible Eh, no resources? How do you talk with the hardware? This looks way too Linuxy... Best regards, Krzysztof
Hi Krzysztof,
On Sat, Nov 23, 2024 at 10:14 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Fri, Nov 22, 2024 at 03:36:23PM +0530, Shubhrajyoti Datta wrote:
> > Add device tree bindings for AMD Versal NET EDAC for DDR controller.
> >
> > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> > ---
> >
>
..
> > +
> > + amd,dwidth:
> > + description:
> > + DDR memory controller device width.
>
> Use existing properties.
I am not finding any existing properties could you help me with some pointers.
>
>
> > + enum: [16, 32]
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + amd,num-chans:
> > + description:
> > + Number of channels.
>
> Use existing properties, e.g. some of the DDR schemas describing memory.
> Look how other bindings describe actual chips.
could you share any example. My search didnt return anything
>
> > + enum: [1, 2]
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + amd,num-rank:
> > + description:
> > + Number of rank.
> > + enum: [1, 2, 4]
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > +required:
> > + - compatible
>
> Eh, no resources? How do you talk with the hardware? This looks way too
> Linuxy...
will add a remote proc property
amd,rproc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the remoteproc_r5 rproc node using which APU interacts
with remote processor.
memory-controller {
...
amd,rproc = <&remoteproc_r5>;
};
>
> Best regards,
> Krzysztof
>
>
On 23/12/2024 10:58, Shubhrajyoti Datta wrote: > Hi Krzysztof, > > On Sat, Nov 23, 2024 at 10:14 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: >> >> On Fri, Nov 22, 2024 at 03:36:23PM +0530, Shubhrajyoti Datta wrote: >>> Add device tree bindings for AMD Versal NET EDAC for DDR controller. >>> >>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> >>> --- >>> >> > .. >>> + >>> + amd,dwidth: >>> + description: >>> + DDR memory controller device width. >> >> Use existing properties. > I am not finding any existing properties could you help me with some pointers. Really? `git grep width` gives plenty of choices, depending on the meaning. I don't know what this property is about - your description is not helping. Either obvious or not correct, because memory controller cannot have a width. Like width in cm? inches? > >> >> >>> + enum: [16, 32] >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + >>> + amd,num-chans: >>> + description: >>> + Number of channels. >> >> Use existing properties, e.g. some of the DDR schemas describing memory. >> Look how other bindings describe actual chips. > > could you share any example. My search didnt return anything I don't believe you tried to search then... There are like 5 bindings describing some parts of memory bus to choose from. There are dedicated bindings for DDR memory - it's all there. Look how other bindings reference JEDEC DDR. Best regards, Krzysztof
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