Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
1 file changed, 198 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 590beb37f441..37c6ab217c96 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -399,6 +399,65 @@ qfprom: efuse@780000 {
#size-cells = <1>;
};
+ sdhc_1: mmc@7c4000 {
+ compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x007c4000 0x0 0x1000>,
+ <0x0 0x007c5000 0x0 0x1000>;
+ reg-names = "hc",
+ "cqhci";
+
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo",
+ "ice";
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+ iommus = <&apps_smmu 0x02c0 0x0>;
+ interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ bus-width = <8>;
+ qcom,dll-config = <0x000f642c>;
+ qcom,ddr-config = <0x80040868>;
+ supports-cqe;
+ dma-coherent;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -494,6 +553,145 @@ qup_uart0_rx: qup-uart0-rx-state {
pins = "gpio17";
function = "qup0";
};
+
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_state_on: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc2_state_off: sdc2-off-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+ };
+
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>;
+ reg-names = "hc";
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ iommus = <&apps_smmu 0x02a0 0x0>;
+ resets = <&gcc GCC_SDCC2_BCR>;
+ interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ bus-width = <4>;
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ dma-coherent;
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
dc_noc: interconnect@9160000 {
--
2.34.1On 22.11.2024 7:51 AM, Yuanjie Yang wrote:
> Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
>
> Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
> 1 file changed, 198 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 590beb37f441..37c6ab217c96 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
> #size-cells = <1>;
> };
>
> + sdhc_1: mmc@7c4000 {
> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x007c4000 0x0 0x1000>,
> + <0x0 0x007c5000 0x0 0x1000>;
> + reg-names = "hc",
> + "cqhci";
There's an "ice" region at 0x007c8000
> +
> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq",
> + "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> + clock-names = "iface",
> + "core",
> + "xo",
> + "ice";
> +
> + resets = <&gcc GCC_SDCC1_BCR>;
> +
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + operating-points-v2 = <&sdhc1_opp_table>;
> + iommus = <&apps_smmu 0x02c0 0x0>;
> + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "sdhc-ddr",
> + "cpu-sdhc";
> +
> + bus-width = <8>;
> + qcom,dll-config = <0x000f642c>;
> + qcom,ddr-config = <0x80040868>;
> + supports-cqe;
> + dma-coherent;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
> + status = "disabled";
> +
> + sdhc1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
I'm seeing 25/50 MHz OPPs in the docs as well
[...]
> +
> + sdhc_2: mmc@8804000 {
> + compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5";
Missing space
> + reg = <0x0 0x08804000 0x0 0x1000>;
> + reg-names = "hc";
> +
> + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq",
> + "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> + <&gcc GCC_SDCC2_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface",
> + "core",
> + "xo";
> +
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + operating-points-v2 = <&sdhc2_opp_table>;
> + iommus = <&apps_smmu 0x02a0 0x0>;
> + resets = <&gcc GCC_SDCC2_BCR>;
> + interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "sdhc-ddr",
> + "cpu-sdhc";
> +
> + bus-width = <4>;
> + qcom,dll-config = <0x0007642c>;
> + qcom,ddr-config = <0x80040868>;
> + dma-coherent;
> + status = "disabled";
> +
> + sdhc2_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
Similarly, it can operate at 25/50 MHz too
Konrad
On Mon, Nov 25, 2024 at 02:13:22PM +0100, Konrad Dybcio wrote:
> On 22.11.2024 7:51 AM, Yuanjie Yang wrote:
> > Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
> >
> > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
> > 1 file changed, 198 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > index 590beb37f441..37c6ab217c96 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
> > #size-cells = <1>;
> > };
> >
> > + sdhc_1: mmc@7c4000 {
> > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> > + reg = <0x0 0x007c4000 0x0 0x1000>,
> > + <0x0 0x007c5000 0x0 0x1000>;
> > + reg-names = "hc",
> > + "cqhci";
>
> There's an "ice" region at 0x007c8000
Thanks, I check doc again, I miss "ice" region at 0x007c8000.
> > +
> > + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hc_irq",
> > + "pwr_irq";
> > +
> > + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> > + <&gcc GCC_SDCC1_APPS_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>,
> > + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> > + clock-names = "iface",
> > + "core",
> > + "xo",
> > + "ice";
> > +
> > + resets = <&gcc GCC_SDCC1_BCR>;
> > +
> > + power-domains = <&rpmhpd RPMHPD_CX>;
> > + operating-points-v2 = <&sdhc1_opp_table>;
> > + iommus = <&apps_smmu 0x02c0 0x0>;
> > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
> > + interconnect-names = "sdhc-ddr",
> > + "cpu-sdhc";
> > +
> > + bus-width = <8>;
> > + qcom,dll-config = <0x000f642c>;
> > + qcom,ddr-config = <0x80040868>;
> > + supports-cqe;
> > + dma-coherent;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + mmc-hs400-1_8v;
> > + mmc-hs400-enhanced-strobe;
> > + status = "disabled";
> > +
> > + sdhc1_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-100000000 {
> > + opp-hz = /bits/ 64 <100000000>;
> > + required-opps = <&rpmhpd_opp_svs>;
> > + };
>
> I'm seeing 25/50 MHz OPPs in the docs as well
Thanks, I check doc again, I miss 50MHz OPPs, but I don't find 25MHz.
> [...]
>
> > +
> > + sdhc_2: mmc@8804000 {
> > + compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5";
>
> Missing space
>
> > + reg = <0x0 0x08804000 0x0 0x1000>;
> > + reg-names = "hc";
> > +
> > + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hc_irq",
> > + "pwr_irq";
> > +
> > + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> > + <&gcc GCC_SDCC2_APPS_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "iface",
> > + "core",
> > + "xo";
> > +
> > + power-domains = <&rpmhpd RPMHPD_CX>;
> > + operating-points-v2 = <&sdhc2_opp_table>;
> > + iommus = <&apps_smmu 0x02a0 0x0>;
> > + resets = <&gcc GCC_SDCC2_BCR>;
> > + interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
> > + interconnect-names = "sdhc-ddr",
> > + "cpu-sdhc";
> > +
> > + bus-width = <4>;
> > + qcom,dll-config = <0x0007642c>;
> > + qcom,ddr-config = <0x80040868>;
> > + dma-coherent;
> > + status = "disabled";
> > +
> > + sdhc2_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
>
> Similarly, it can operate at 25/50 MHz too
Thanks, I check doc again, I miss 50MHz OPPs, but I don't find 25MHz.
>
> Konrad
Thanks,
Yuanjie
On Tue, Nov 26, 2024 at 05:07:11PM +0800, Yuanjie Yang wrote:
> On Mon, Nov 25, 2024 at 02:13:22PM +0100, Konrad Dybcio wrote:
> > On 22.11.2024 7:51 AM, Yuanjie Yang wrote:
> > > Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
> > >
> > > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
> > > 1 file changed, 198 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > > index 590beb37f441..37c6ab217c96 100644
> > > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > > @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
> > > #size-cells = <1>;
> > > };
> > >
> > > + sdhc_1: mmc@7c4000 {
> > > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> > > + reg = <0x0 0x007c4000 0x0 0x1000>,
> > > + <0x0 0x007c5000 0x0 0x1000>;
> > > + reg-names = "hc",
> > > + "cqhci";
> >
> > There's an "ice" region at 0x007c8000
> Thanks, I check doc again, I miss "ice" region at 0x007c8000.
>
> > > +
> > > + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> > > + interrupt-names = "hc_irq",
> > > + "pwr_irq";
> > > +
> > > + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> > > + <&gcc GCC_SDCC1_APPS_CLK>,
> > > + <&rpmhcc RPMH_CXO_CLK>,
> > > + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> > > + clock-names = "iface",
> > > + "core",
> > > + "xo",
> > > + "ice";
> > > +
> > > + resets = <&gcc GCC_SDCC1_BCR>;
> > > +
> > > + power-domains = <&rpmhpd RPMHPD_CX>;
> > > + operating-points-v2 = <&sdhc1_opp_table>;
> > > + iommus = <&apps_smmu 0x02c0 0x0>;
> > > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
> > > + interconnect-names = "sdhc-ddr",
> > > + "cpu-sdhc";
> > > +
> > > + bus-width = <8>;
> > > + qcom,dll-config = <0x000f642c>;
> > > + qcom,ddr-config = <0x80040868>;
> > > + supports-cqe;
> > > + dma-coherent;
> > > + mmc-ddr-1_8v;
> > > + mmc-hs200-1_8v;
> > > + mmc-hs400-1_8v;
> > > + mmc-hs400-enhanced-strobe;
> > > + status = "disabled";
> > > +
> > > + sdhc1_opp_table: opp-table {
> > > + compatible = "operating-points-v2";
> > > +
> > > + opp-100000000 {
> > > + opp-hz = /bits/ 64 <100000000>;
> > > + required-opps = <&rpmhpd_opp_svs>;
> > > + };
> >
> > I'm seeing 25/50 MHz OPPs in the docs as well
> Thanks, I check doc again, I miss 50MHz OPPs, but I don't find 25MHz.
>
> > [...]
> >
> > > +
> > > + sdhc_2: mmc@8804000 {
> > > + compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5";
> >
> > Missing space
Thanks, I will add space in next version.
> > > + reg = <0x0 0x08804000 0x0 0x1000>;
> > > + reg-names = "hc";
> > > +
> > > + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> > > + interrupt-names = "hc_irq",
> > > + "pwr_irq";
> > > +
> > > + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> > > + <&gcc GCC_SDCC2_APPS_CLK>,
> > > + <&rpmhcc RPMH_CXO_CLK>;
> > > + clock-names = "iface",
> > > + "core",
> > > + "xo";
> > > +
> > > + power-domains = <&rpmhpd RPMHPD_CX>;
> > > + operating-points-v2 = <&sdhc2_opp_table>;
> > > + iommus = <&apps_smmu 0x02a0 0x0>;
> > > + resets = <&gcc GCC_SDCC2_BCR>;
> > > + interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
> > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > > + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
> > > + interconnect-names = "sdhc-ddr",
> > > + "cpu-sdhc";
> > > +
> > > + bus-width = <4>;
> > > + qcom,dll-config = <0x0007642c>;
> > > + qcom,ddr-config = <0x80040868>;
> > > + dma-coherent;
> > > + status = "disabled";
> > > +
> > > + sdhc2_opp_table: opp-table {
> > > + compatible = "operating-points-v2";
> > > +
> >
> > Similarly, it can operate at 25/50 MHz too
> Thanks, I check doc again, I miss 50MHz OPPs, but I don't find 25MHz.
>
> >
> > Konrad
>
> Thanks,
> Yuanjie
>
Thanks,
Yuanjie
On Mon, Nov 25, 2024 at 02:13:22PM +0100, Konrad Dybcio wrote:
> On 22.11.2024 7:51 AM, Yuanjie Yang wrote:
> > Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
> >
> > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
> > 1 file changed, 198 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > index 590beb37f441..37c6ab217c96 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
> > #size-cells = <1>;
> > };
> >
> > + sdhc_1: mmc@7c4000 {
> > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> > + reg = <0x0 0x007c4000 0x0 0x1000>,
> > + <0x0 0x007c5000 0x0 0x1000>;
> > + reg-names = "hc",
> > + "cqhci";
>
> There's an "ice" region at 0x007c8000
Shouldn't ice now be handled by a separate device?
--
With best wishes
Dmitry
On 26/11/2024 01:07, Dmitry Baryshkov wrote:
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> index 590beb37f441..37c6ab217c96 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
>>> #size-cells = <1>;
>>> };
>>>
>>> + sdhc_1: mmc@7c4000 {
>>> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
>>> + reg = <0x0 0x007c4000 0x0 0x1000>,
>>> + <0x0 0x007c5000 0x0 0x1000>;
>>> + reg-names = "hc",
>>> + "cqhci";
>>
>> There's an "ice" region at 0x007c8000
>
> Shouldn't ice now be handled by a separate device?
It should and UFS bindings expect that. However I am not sure if MMC was
improved to support external ICE device. Also for example on SM8550 the
ICE has entirely different (further) address space, so it also suggests
it is separate device. Here address space looks almost continuous.
Best regards,
Krzysztof
On 26.11.2024 10:26 AM, Krzysztof Kozlowski wrote:
> On 26/11/2024 01:07, Dmitry Baryshkov wrote:
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> index 590beb37f441..37c6ab217c96 100644
>>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
>>>> #size-cells = <1>;
>>>> };
>>>>
>>>> + sdhc_1: mmc@7c4000 {
>>>> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
>>>> + reg = <0x0 0x007c4000 0x0 0x1000>,
>>>> + <0x0 0x007c5000 0x0 0x1000>;
>>>> + reg-names = "hc",
>>>> + "cqhci";
>>>
>>> There's an "ice" region at 0x007c8000
>>
>> Shouldn't ice now be handled by a separate device?
> It should and UFS bindings expect that. However I am not sure if MMC was
> improved to support external ICE device. Also for example on SM8550 the
> ICE has entirely different (further) address space, so it also suggests
> it is separate device. Here address space looks almost continuous.
Some SoCs have two ICEs (one for UFS and one for SDHCI) - seems to be
mainly the case on platforms where there's "sdhc1" (intended for eMMC)
*and* a UFS host.
The commit message that introduced a separate driver says:
"""
The reason for this is because, staring with SM8550, the ICE IP block
is shared between UFS and SDCC, which means we need to probe a dedicated
device and share it between those two consumers.
"""
but:
* in sm8550.dtsi, only UFS has a qcom,ice reference (like other device
trees using that binding)
* I can't find anything that would back this internally
I'm not sure how this is supposed to work, especially on SoCs with two
instances
Konrad
On 22/11/2024 07:51, Yuanjie Yang wrote:
> Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
>
> Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
> 1 file changed, 198 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 590beb37f441..37c6ab217c96 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
> #size-cells = <1>;
> };
>
> + sdhc_1: mmc@7c4000 {
> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x007c4000 0x0 0x1000>,
> + <0x0 0x007c5000 0x0 0x1000>;
> + reg-names = "hc",
> + "cqhci";
> +
> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq",
> + "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> + clock-names = "iface",
> + "core",
> + "xo",
> + "ice";
> +
> + resets = <&gcc GCC_SDCC1_BCR>;
> +
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + operating-points-v2 = <&sdhc1_opp_table>;
> + iommus = <&apps_smmu 0x02c0 0x0>;
> + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "sdhc-ddr",
> + "cpu-sdhc";
> +
> + bus-width = <8>;
> + qcom,dll-config = <0x000f642c>;
> + qcom,ddr-config = <0x80040868>;
> + supports-cqe;
> + dma-coherent;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
These are properties of memory, not SoC. If the node is disabled, means
memory is not attached to the SoC, right?
> + status = "disabled";
...
> +
> + sdhc_2: mmc@8804000 {
> + compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5";
> + reg = <0x0 0x08804000 0x0 0x1000>;
> + reg-names = "hc";
> +
> + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq",
> + "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> + <&gcc GCC_SDCC2_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface",
> + "core",
> + "xo";
> +
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + operating-points-v2 = <&sdhc2_opp_table>;
> + iommus = <&apps_smmu 0x02a0 0x0>;
> + resets = <&gcc GCC_SDCC2_BCR>;
> + interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "sdhc-ddr",
> + "cpu-sdhc";
> +
> + bus-width = <4>;
Same comments.
> + qcom,dll-config = <0x0007642c>;
> + qcom,ddr-config = <0x80040868>;
> + dma-coherent;
> + status = "disabled";
> +
> + sdhc2_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-202000000 {
> + opp-hz = /bits/ 64 <202000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> };
>
> dc_noc: interconnect@9160000 {
Best regards,
Krzysztof
On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote:
> On 22/11/2024 07:51, Yuanjie Yang wrote:
> > Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
> >
> > Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
> > 1 file changed, 198 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > index 590beb37f441..37c6ab217c96 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
> > #size-cells = <1>;
> > };
> >
> > + sdhc_1: mmc@7c4000 {
> > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> > + reg = <0x0 0x007c4000 0x0 0x1000>,
> > + <0x0 0x007c5000 0x0 0x1000>;
> > + reg-names = "hc",
> > + "cqhci";
> > +
> > + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hc_irq",
> > + "pwr_irq";
> > +
> > + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> > + <&gcc GCC_SDCC1_APPS_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>,
> > + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> > + clock-names = "iface",
> > + "core",
> > + "xo",
> > + "ice";
> > +
> > + resets = <&gcc GCC_SDCC1_BCR>;
> > +
> > + power-domains = <&rpmhpd RPMHPD_CX>;
> > + operating-points-v2 = <&sdhc1_opp_table>;
> > + iommus = <&apps_smmu 0x02c0 0x0>;
> > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
> > + interconnect-names = "sdhc-ddr",
> > + "cpu-sdhc";
> > +
> > + bus-width = <8>;
> > + qcom,dll-config = <0x000f642c>;
> > + qcom,ddr-config = <0x80040868>;
> > + supports-cqe;
> > + dma-coherent;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + mmc-hs400-1_8v;
> > + mmc-hs400-enhanced-strobe;
>
> These are properties of memory, not SoC. If the node is disabled, means
> memory is not attached to the SoC, right?
>
> > + status = "disabled";
Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc,
they are memory configurations that need to be written to the ioaddr.
And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config,
they indicate the bus speed at which the host contoller can operate.
If the node is disabled, which means Soc don't support these properties.
>
>
> ...
>
> > +
> > + sdhc_2: mmc@8804000 {
> > + compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5";
> > + reg = <0x0 0x08804000 0x0 0x1000>;
> > + reg-names = "hc";
> > +
> > + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hc_irq",
> > + "pwr_irq";
> > +
> > + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> > + <&gcc GCC_SDCC2_APPS_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "iface",
> > + "core",
> > + "xo";
> > +
> > + power-domains = <&rpmhpd RPMHPD_CX>;
> > + operating-points-v2 = <&sdhc2_opp_table>;
> > + iommus = <&apps_smmu 0x02a0 0x0>;
> > + resets = <&gcc GCC_SDCC2_BCR>;
> > + interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
> > + interconnect-names = "sdhc-ddr",
> > + "cpu-sdhc";
> > +
> > + bus-width = <4>;
>
> Same comments.
Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc,
they are memory configurations that need to be written to the ioaddr.
And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config,
they indicate the bus speed at which the host controller can operate.
If the node is disabled, which means Soc don't support these properties.
> > + qcom,dll-config = <0x0007642c>;
> > + qcom,ddr-config = <0x80040868>;
> > + dma-coherent;
> > + status = "disabled";
> > +
> > + sdhc2_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-100000000 {
> > + opp-hz = /bits/ 64 <100000000>;
> > + required-opps = <&rpmhpd_opp_low_svs>;
> > + };
> > +
> > + opp-202000000 {
> > + opp-hz = /bits/ 64 <202000000>;
> > + required-opps = <&rpmhpd_opp_nom>;
> > + };
> > + };
> > };
> >
> > dc_noc: interconnect@9160000 {
>
>
> Best regards,
> Krzysztof
Thanks,
Yuanjie
On 22/11/2024 09:40, Yuanjie Yang wrote:
> On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote:
>> On 22/11/2024 07:51, Yuanjie Yang wrote:
>>> Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
>>>
>>> Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
>>> 1 file changed, 198 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> index 590beb37f441..37c6ab217c96 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
>>> #size-cells = <1>;
>>> };
>>>
>>> + sdhc_1: mmc@7c4000 {
>>> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
>>> + reg = <0x0 0x007c4000 0x0 0x1000>,
>>> + <0x0 0x007c5000 0x0 0x1000>;
>>> + reg-names = "hc",
>>> + "cqhci";
>>> +
>>> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupt-names = "hc_irq",
>>> + "pwr_irq";
>>> +
>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>>> + <&gcc GCC_SDCC1_APPS_CLK>,
>>> + <&rpmhcc RPMH_CXO_CLK>,
>>> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
>>> + clock-names = "iface",
>>> + "core",
>>> + "xo",
>>> + "ice";
>>> +
>>> + resets = <&gcc GCC_SDCC1_BCR>;
>>> +
>>> + power-domains = <&rpmhpd RPMHPD_CX>;
>>> + operating-points-v2 = <&sdhc1_opp_table>;
>>> + iommus = <&apps_smmu 0x02c0 0x0>;
>>> + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
>>> + interconnect-names = "sdhc-ddr",
>>> + "cpu-sdhc";
>>> +
>>> + bus-width = <8>;
>>> + qcom,dll-config = <0x000f642c>;
>>> + qcom,ddr-config = <0x80040868>;
>>> + supports-cqe;
>>> + dma-coherent;
>>> + mmc-ddr-1_8v;
>>> + mmc-hs200-1_8v;
>>> + mmc-hs400-1_8v;
>>> + mmc-hs400-enhanced-strobe;
>>
>> These are properties of memory, not SoC. If the node is disabled, means
>> memory is not attached to the SoC, right?
>>
>>> + status = "disabled";
> Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc,
> they are memory configurations that need to be written to the ioaddr.
> And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config,
> they indicate the bus speed at which the host contoller can operate.
> If the node is disabled, which means Soc don't support these properties.
No, that is not the meaning of node is disabled. When node is disabled,
it means board does not have attached memory.
Move the memory related properties to the board.
Best regards,
Krzysztof
On Fri, Nov 22, 2024 at 01:35:28PM +0100, Krzysztof Kozlowski wrote:
> On 22/11/2024 09:40, Yuanjie Yang wrote:
> > On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote:
> >> On 22/11/2024 07:51, Yuanjie Yang wrote:
> >>> Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
> >>>
> >>> Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
> >>> ---
> >>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
> >>> 1 file changed, 198 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> >>> index 590beb37f441..37c6ab217c96 100644
> >>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> >>> @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
> >>> #size-cells = <1>;
> >>> };
> >>>
> >>> + sdhc_1: mmc@7c4000 {
> >>> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> >>> + reg = <0x0 0x007c4000 0x0 0x1000>,
> >>> + <0x0 0x007c5000 0x0 0x1000>;
> >>> + reg-names = "hc",
> >>> + "cqhci";
> >>> +
> >>> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> >>> + interrupt-names = "hc_irq",
> >>> + "pwr_irq";
> >>> +
> >>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> >>> + <&gcc GCC_SDCC1_APPS_CLK>,
> >>> + <&rpmhcc RPMH_CXO_CLK>,
> >>> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> >>> + clock-names = "iface",
> >>> + "core",
> >>> + "xo",
> >>> + "ice";
> >>> +
> >>> + resets = <&gcc GCC_SDCC1_BCR>;
> >>> +
> >>> + power-domains = <&rpmhpd RPMHPD_CX>;
> >>> + operating-points-v2 = <&sdhc1_opp_table>;
> >>> + iommus = <&apps_smmu 0x02c0 0x0>;
> >>> + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> >>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> >>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> >>> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
> >>> + interconnect-names = "sdhc-ddr",
> >>> + "cpu-sdhc";
> >>> +
> >>> + bus-width = <8>;
> >>> + qcom,dll-config = <0x000f642c>;
> >>> + qcom,ddr-config = <0x80040868>;
> >>> + supports-cqe;
> >>> + dma-coherent;
> >>> + mmc-ddr-1_8v;
> >>> + mmc-hs200-1_8v;
> >>> + mmc-hs400-1_8v;
> >>> + mmc-hs400-enhanced-strobe;
> >>
> >> These are properties of memory, not SoC. If the node is disabled, means
> >> memory is not attached to the SoC, right?
> >>
> >>> + status = "disabled";
> > Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc,
> > they are memory configurations that need to be written to the ioaddr.
> > And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config,
> > they indicate the bus speed at which the host contoller can operate.
> > If the node is disabled, which means Soc don't support these properties.
> No, that is not the meaning of node is disabled. When node is disabled,
> it means board does not have attached memory.
>
> Move the memory related properties to the board.
Thanks, Ok I understand, I will move the memory related
properties(qcom,dll-config and qcom,ddr-config) to the
board dts in next version.
> Best regards,
> Krzysztof
Thanks,
Yuanjie
On 25.11.2024 3:20 AM, Yuanjie Yang wrote: > On Fri, Nov 22, 2024 at 01:35:28PM +0100, Krzysztof Kozlowski wrote: >> On 22/11/2024 09:40, Yuanjie Yang wrote: >>> On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote: >>>> On 22/11/2024 07:51, Yuanjie Yang wrote: >>>>> Add SDHC1 and SDHC2 support to the QCS615 Ride platform. >>>>> >>>>> Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> >>>>> --- [...] >>>>> + bus-width = <8>; >>>>> + qcom,dll-config = <0x000f642c>; >>>>> + qcom,ddr-config = <0x80040868>; >>>>> + supports-cqe; >>>>> + dma-coherent; >>>>> + mmc-ddr-1_8v; >>>>> + mmc-hs200-1_8v; >>>>> + mmc-hs400-1_8v; >>>>> + mmc-hs400-enhanced-strobe; >>>> >>>> These are properties of memory, not SoC. If the node is disabled, means >>>> memory is not attached to the SoC, right? >>>> >>>>> + status = "disabled"; >>> Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc, >>> they are memory configurations that need to be written to the ioaddr. >>> And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config, >>> they indicate the bus speed at which the host contoller can operate. >>> If the node is disabled, which means Soc don't support these properties. >> No, that is not the meaning of node is disabled. When node is disabled, >> it means board does not have attached memory. >> >> Move the memory related properties to the board. > > Thanks, Ok I understand, I will move the memory related > properties(qcom,dll-config and qcom,ddr-config) to the > board dts in next version. DDR/DLL tuning seem to be done per SoC and not per board. Konrad
On 25/11/2024 03:20, Yuanjie Yang wrote:
> On Fri, Nov 22, 2024 at 01:35:28PM +0100, Krzysztof Kozlowski wrote:
>> On 22/11/2024 09:40, Yuanjie Yang wrote:
>>> On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote:
>>>> On 22/11/2024 07:51, Yuanjie Yang wrote:
>>>>> Add SDHC1 and SDHC2 support to the QCS615 Ride platform.
>>>>>
>>>>> Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
>>>>> 1 file changed, 198 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>> index 590beb37f441..37c6ab217c96 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>>> @@ -399,6 +399,65 @@ qfprom: efuse@780000 {
>>>>> #size-cells = <1>;
>>>>> };
>>>>>
>>>>> + sdhc_1: mmc@7c4000 {
>>>>> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
>>>>> + reg = <0x0 0x007c4000 0x0 0x1000>,
>>>>> + <0x0 0x007c5000 0x0 0x1000>;
>>>>> + reg-names = "hc",
>>>>> + "cqhci";
>>>>> +
>>>>> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
>>>>> + interrupt-names = "hc_irq",
>>>>> + "pwr_irq";
>>>>> +
>>>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>>>>> + <&gcc GCC_SDCC1_APPS_CLK>,
>>>>> + <&rpmhcc RPMH_CXO_CLK>,
>>>>> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
>>>>> + clock-names = "iface",
>>>>> + "core",
>>>>> + "xo",
>>>>> + "ice";
>>>>> +
>>>>> + resets = <&gcc GCC_SDCC1_BCR>;
>>>>> +
>>>>> + power-domains = <&rpmhpd RPMHPD_CX>;
>>>>> + operating-points-v2 = <&sdhc1_opp_table>;
>>>>> + iommus = <&apps_smmu 0x02c0 0x0>;
>>>>> + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
>>>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>>>> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
>>>>> + interconnect-names = "sdhc-ddr",
>>>>> + "cpu-sdhc";
>>>>> +
>>>>> + bus-width = <8>;
>>>>> + qcom,dll-config = <0x000f642c>;
>>>>> + qcom,ddr-config = <0x80040868>;
>>>>> + supports-cqe;
>>>>> + dma-coherent;
>>>>> + mmc-ddr-1_8v;
>>>>> + mmc-hs200-1_8v;
>>>>> + mmc-hs400-1_8v;
>>>>> + mmc-hs400-enhanced-strobe;
>>>>
>>>> These are properties of memory, not SoC. If the node is disabled, means
>>>> memory is not attached to the SoC, right?
>>>>
>>>>> + status = "disabled";
>>> Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc,
>>> they are memory configurations that need to be written to the ioaddr.
>>> And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config,
>>> they indicate the bus speed at which the host contoller can operate.
>>> If the node is disabled, which means Soc don't support these properties.
>> No, that is not the meaning of node is disabled. When node is disabled,
>> it means board does not have attached memory.
>>
>> Move the memory related properties to the board.
>
> Thanks, Ok I understand, I will move the memory related
> properties(qcom,dll-config and qcom,ddr-config) to the
> board dts in next version.
What? Why are you talking about these properties? My comment was not
under these!
Best regards,
Krzysztof
© 2016 - 2026 Red Hat, Inc.