Add the Global Command Engine (GCE) header file to define the GCE
thread priority, GCE subsys ID, GCE events, and various constants
for MT8196.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
---
.../dt-bindings/mailbox/mediatek,mt8196-gce.h | 1449 +++++++++++++++++
1 file changed, 1449 insertions(+)
create mode 100755 include/dt-bindings/mailbox/mediatek,mt8196-gce.h
diff --git a/include/dt-bindings/mailbox/mediatek,mt8196-gce.h b/include/dt-bindings/mailbox/mediatek,mt8196-gce.h
new file mode 100755
index 000000000000..371058b637de
--- /dev/null
+++ b/include/dt-bindings/mailbox/mediatek,mt8196-gce.h
@@ -0,0 +1,1449 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2024 MediaTek Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_GCE_MT8196_H
+#define _DT_BINDINGS_GCE_MT8196_H
+
+/* Assign timeout to 0 means default */
+#define CMDQ_NO_TIMEOUT 0xffffffff
+#define CMDQ_TIMEOUT_DEFAULT 1000
+
+/* GCE thread priority */
+#define CMDQ_THR_PRIO_LOWEST 0
+#define CMDQ_THR_PRIO_1 1
+#define CMDQ_THR_PRIO_2 2
+#define CMDQ_THR_PRIO_3 3
+#define CMDQ_THR_PRIO_4 4
+#define CMDQ_THR_PRIO_5 5
+#define CMDQ_THR_PRIO_6 6
+#define CMDQ_THR_PRIO_HIGHEST 7
+
+/* CPR count in 32-bit register */
+#define GCE_CPR_COUNT 1312
+
+/* GCE subsys table */
+#define SUBSYS_1300XXXX 0
+#define SUBSYS_1400XXXX 1
+#define SUBSYS_1401XXXX 2
+#define SUBSYS_1402XXXX 3
+#define SUBSYS_1502XXXX 4
+#define SUBSYS_1880XXXX 5
+#define SUBSYS_1881XXXX 6
+#define SUBSYS_1882XXXX 7
+#define SUBSYS_1883XXXX 8
+#define SUBSYS_1884XXXX 9
+#define SUBSYS_1000XXXX 10
+#define SUBSYS_1001XXXX 11
+#define SUBSYS_1002XXXX 12
+#define SUBSYS_1003XXXX 13
+#define SUBSYS_1004XXXX 14
+#define SUBSYS_1005XXXX 15
+#define SUBSYS_1020XXXX 16
+#define SUBSYS_1028XXXX 17
+#define SUBSYS_1700XXXX 18
+#define SUBSYS_1701XXXX 19
+#define SUBSYS_1702XXXX 20
+#define SUBSYS_1703XXXX 21
+#define SUBSYS_1800XXXX 22
+#define SUBSYS_1801XXXX 23
+#define SUBSYS_1802XXXX 24
+#define SUBSYS_1804XXXX 25
+#define SUBSYS_1805XXXX 26
+#define SUBSYS_1808XXXX 27
+#define SUBSYS_180aXXXX 28
+#define SUBSYS_180bXXXX 29
+#define SUBSYS_NO_SUPPORT 99
+
+/*
+ * GCE General Purpose Register (GPR) support
+ * Leave note for scenario usage here
+ */
+/* GCE: write mask */
+#define GCE_GPR_R00 0x0
+#define GCE_GPR_R01 0x1
+/* Configurable GPR for hardware module */
+#define GCE_GPR_R02 0x2
+#define GCE_GPR_R03 0x3
+#define GCE_GPR_R04 0x4
+#define GCE_GPR_R05 0x5
+#define GCE_GPR_R06 0x6
+#define GCE_GPR_R07 0x7
+#define GCE_GPR_R08 0x8
+#define GCE_GPR_R09 0x9
+#define GCE_GPR_R10 0xa
+#define GCE_GPR_R11 0xb
+#define GCE_GPR_R12 0xc
+#define GCE_GPR_R13 0xd
+/* CMDQ: for generating instruction */
+#define GCE_GPR_R14 0xe
+#define GCE_GPR_R15 0xf
+
+/* GCE-D hardware events */
+#define CMDQ_EVENT_DISP0_STREAM_SOF0 0
+#define CMDQ_EVENT_DISP0_STREAM_SOF1 1
+#define CMDQ_EVENT_DISP0_STREAM_SOF2 2
+#define CMDQ_EVENT_DISP0_STREAM_SOF3 3
+#define CMDQ_EVENT_DISP0_STREAM_SOF4 4
+#define CMDQ_EVENT_DISP0_STREAM_SOF5 5
+#define CMDQ_EVENT_DISP0_STREAM_SOF6 6
+#define CMDQ_EVENT_DISP0_STREAM_SOF7 7
+#define CMDQ_EVENT_DISP0_STREAM_SOF8 8
+#define CMDQ_EVENT_DISP0_STREAM_SOF9 9
+#define CMDQ_EVENT_DISP0_STREAM_SOF10 10
+#define CMDQ_EVENT_DISP0_STREAM_SOF11 11
+#define CMDQ_EVENT_DISP0_STREAM_SOF12 12
+#define CMDQ_EVENT_DISP0_STREAM_SOF13 13
+#define CMDQ_EVENT_DISP0_STREAM_SOF14 14
+#define CMDQ_EVENT_DISP0_STREAM_SOF15 15
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL0 16
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL1 17
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL2 18
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL3 19
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL4 20
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL5 21
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL6 22
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL7 23
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL8 24
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL9 25
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL10 26
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL11 27
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL12 28
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL13 29
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL14 30
+#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL15 31
+#define CMDQ_EVENT_DISP0_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 32
+#define CMDQ_EVENT_DISP0_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 33
+#define CMDQ_EVENT_DISP0_DISP_POSTMASK1_RST_DONE_ENG_EVENT 34
+#define CMDQ_EVENT_DISP0_DISP_POSTMASK0_RST_DONE_ENG_EVENT 35
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_TIMEOUT_ENG_EVENT 36
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT0 37
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT1 38
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT2 39
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT3 40
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT4 41
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT5 42
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT6 43
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT7 44
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT8 45
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT9 46
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT10 47
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT11 48
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT12 49
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT13 50
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT14 51
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT15 52
+#define CMDQ_EVENT_DISP0_DISP_MUTEX0_GET_RELEASE_ENG_EVENT 53
+#define CMDQ_EVENT_DISP0_DISP_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 54
+
+#define CMDQ_EVENT_DISP1_STREAM_SOF0 55
+#define CMDQ_EVENT_DISP1_STREAM_SOF1 56
+#define CMDQ_EVENT_DISP1_STREAM_SOF2 57
+#define CMDQ_EVENT_DISP1_STREAM_SOF3 58
+#define CMDQ_EVENT_DISP1_STREAM_SOF4 59
+#define CMDQ_EVENT_DISP1_STREAM_SOF5 60
+#define CMDQ_EVENT_DISP1_STREAM_SOF6 61
+#define CMDQ_EVENT_DISP1_STREAM_SOF7 62
+#define CMDQ_EVENT_DISP1_STREAM_SOF8 63
+#define CMDQ_EVENT_DISP1_STREAM_SOF9 64
+#define CMDQ_EVENT_DISP1_STREAM_SOF10 65
+#define CMDQ_EVENT_DISP1_STREAM_SOF11 66
+#define CMDQ_EVENT_DISP1_STREAM_SOF12 67
+#define CMDQ_EVENT_DISP1_STREAM_SOF13 68
+#define CMDQ_EVENT_DISP1_STREAM_SOF14 69
+#define CMDQ_EVENT_DISP1_STREAM_SOF15 70
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL0 71
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL1 72
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL2 73
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL3 74
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL4 75
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL5 76
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL6 77
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL7 78
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL8 79
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL9 80
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL10 81
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL11 82
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL12 83
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL13 84
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL14 85
+#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL15 86
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT0 87
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT1 88
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT2 89
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT3 90
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT4 91
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT5 92
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT6 93
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT7 94
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT8 95
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT9 96
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT10 97
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT11 98
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT12 99
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT13 100
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT14 101
+#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT15 102
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT0 103
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT1 104
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT2 105
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT3 106
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT4 107
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT5 108
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT6 109
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT7 110
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT8 111
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT9 112
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT10 113
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT11 114
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT12 115
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT13 116
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT14 117
+#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT15 118
+#define CMDQ_EVENT_DISP1_OCIP_SUBSYS_SRAM_ISOINT_ENG_EVENT 119
+#define CMDQ_EVENT_DISP1_DISP_WDMA4_TARGET_LINE_END_ENG_EVENT 120
+#define CMDQ_EVENT_DISP1_DISP_WDMA4_SW_RST_DONE_ENG_EVENT 121
+#define CMDQ_EVENT_DISP1_DISP_WDMA3_TARGET_LINE_END_ENG_EVENT 122
+#define CMDQ_EVENT_DISP1_DISP_WDMA3_SW_RST_DONE_ENG_EVENT 123
+#define CMDQ_EVENT_DISP1_DISP_WDMA2_TARGET_LINE_END_ENG_EVENT 124
+#define CMDQ_EVENT_DISP1_DISP_WDMA2_SW_RST_DONE_ENG_EVENT 125
+#define CMDQ_EVENT_DISP1_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 126
+#define CMDQ_EVENT_DISP1_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 127
+#define CMDQ_EVENT_DISP1_DISP_MUTEX0_TIMEOUT_ENG_EVENT 128
+#define CMDQ_EVENT_DISP1_DISP_MUTEX0_GET_RLZ_ENG_EVENT 129
+#define CMDQ_EVENT_DISP1_DISP_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 130
+#define CMDQ_EVENT_DISP1_DISP_GDMA0_SW_RST_DONE_ENG_EVENT 131
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_START_ENG_EVENT 132
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_END_ENG_EVENT 133
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VRR_VFP_LAST_SAFE_BLANK_ENG_EVENT 134
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_START_ENG_EVENT 135
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_LAST_LINE_ENG_EVENT 136
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VDE_END_ENG_EVENT 137
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TRIGGER_LOOP_CLR_ENG_EVENT 138
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE1_ENG_EVENT 139
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE0_ENG_EVENT 140
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_START_ENG_EVENT 141
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_END_ENG_EVENT 142
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_START_ENG_EVENT 143
+#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_END_ENG_EVENT 144
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT0 145
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT1 146
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT2 147
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT3 148
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT4 149
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT5 150
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT6 151
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT7 152
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT8 153
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT9 154
+#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT10 155
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT0 156
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT1 157
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT2 158
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT3 159
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT4 160
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT5 161
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT6 162
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT7 163
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT8 164
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT9 165
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT10 166
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT11 167
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT12 168
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT13 169
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT14 170
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT15 171
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT16 172
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT17 173
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT18 174
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT19 175
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT20 176
+#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT21 177
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT0 178
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT1 179
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT2 180
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT3 181
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT4 182
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT5 183
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT6 184
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT7 185
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT8 186
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT9 187
+#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT10 188
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_START_ENG_EVENT 189
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_END_ENG_EVENT 190
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_START_ENG_EVENT 191
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_END_ENG_EVENT 192
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_TARGET_LINE_ENG_EVENT 193
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_START_ENG_EVENT 194
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_END_ENG_EVENT 195
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_START_ENG_EVENT 196
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_END_ENG_EVENT 197
+#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_TARGET_LINE_ENG_EVENT 198
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT0 199
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT1 200
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT2 201
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT3 202
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT4 203
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT5 204
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT6 205
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT7 206
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT8 207
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT9 208
+#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT10 209
+
+#define CMDQ_EVENT_MML0_STREAM_SOF0 210
+#define CMDQ_EVENT_MML0_STREAM_SOF1 211
+#define CMDQ_EVENT_MML0_STREAM_SOF2 212
+#define CMDQ_EVENT_MML0_STREAM_SOF3 213
+#define CMDQ_EVENT_MML0_STREAM_SOF4 214
+#define CMDQ_EVENT_MML0_STREAM_SOF5 215
+#define CMDQ_EVENT_MML0_STREAM_SOF6 216
+#define CMDQ_EVENT_MML0_STREAM_SOF7 217
+#define CMDQ_EVENT_MML0_STREAM_SOF8 218
+#define CMDQ_EVENT_MML0_STREAM_SOF9 219
+#define CMDQ_EVENT_MML0_STREAM_SOF10 220
+#define CMDQ_EVENT_MML0_STREAM_SOF11 221
+#define CMDQ_EVENT_MML0_STREAM_SOF12 222
+#define CMDQ_EVENT_MML0_STREAM_SOF13 223
+#define CMDQ_EVENT_MML0_STREAM_SOF14 224
+#define CMDQ_EVENT_MML0_STREAM_SOF15 225
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL0 226
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL1 227
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL2 228
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL3 229
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL4 230
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL5 231
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL6 232
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL7 233
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL8 234
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL9 235
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL10 236
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL11 237
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL12 238
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL13 239
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL14 240
+#define CMDQ_EVENT_MML0_FRAME_DONE_SEL15 241
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT0 242
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT1 243
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT2 244
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT3 245
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT4 246
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT5 247
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT6 248
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT7 249
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT8 250
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT9 251
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT10 252
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT11 253
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT12 254
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT13 255
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT14 256
+#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT15 257
+#define CMDQ_EVENT_MML0_MDP_WROT2_SW_RST_DONE_ENG_EVENT 258
+#define CMDQ_EVENT_MML0_MDP_WROT1_SW_RST_DONE_ENG_EVENT 259
+#define CMDQ_EVENT_MML0_MDP_WROT0_SW_RST_DONE_ENG_EVENT 260
+#define CMDQ_EVENT_MML0_MDP_RROT0_SW_RST_DONE_ENG_EVENT 261
+#define CMDQ_EVENT_MML0_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 262
+#define CMDQ_EVENT_MML0_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 263
+#define CMDQ_EVENT_MML0_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 264
+#define CMDQ_EVENT_MML0_MDP_MERGE0_SW_RST_DONE_ENG_EVENT 265
+#define CMDQ_EVENT_MML0_DISP_MUTEX0_TIMEOUT_ENG_EVENT 266
+#define CMDQ_EVENT_MML0_DISP_MUTEX0_GET_RLZ_ENG_EVENT 267
+
+#define CMDQ_EVENT_MML1_STREAM_SOF0 268
+#define CMDQ_EVENT_MML1_STREAM_SOF1 269
+#define CMDQ_EVENT_MML1_STREAM_SOF2 270
+#define CMDQ_EVENT_MML1_STREAM_SOF3 271
+#define CMDQ_EVENT_MML1_STREAM_SOF4 272
+#define CMDQ_EVENT_MML1_STREAM_SOF5 273
+#define CMDQ_EVENT_MML1_STREAM_SOF6 274
+#define CMDQ_EVENT_MML1_STREAM_SOF7 275
+#define CMDQ_EVENT_MML1_STREAM_SOF8 276
+#define CMDQ_EVENT_MML1_STREAM_SOF9 277
+#define CMDQ_EVENT_MML1_STREAM_SOF10 278
+#define CMDQ_EVENT_MML1_STREAM_SOF11 279
+#define CMDQ_EVENT_MML1_STREAM_SOF12 280
+#define CMDQ_EVENT_MML1_STREAM_SOF13 281
+#define CMDQ_EVENT_MML1_STREAM_SOF14 282
+#define CMDQ_EVENT_MML1_STREAM_SOF15 283
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL0 284
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL1 285
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL2 286
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL3 287
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL4 288
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL5 289
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL6 290
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL7 291
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL8 292
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL9 293
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL10 294
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL11 295
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL12 296
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL13 297
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL14 298
+#define CMDQ_EVENT_MML1_FRAME_DONE_SEL15 299
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT0 300
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT1 301
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT2 302
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT3 303
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT4 304
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT5 305
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT6 306
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT7 307
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT8 308
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT9 309
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT10 310
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT11 311
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT12 312
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT13 313
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT14 314
+#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT15 315
+#define CMDQ_EVENT_MML1_MDP_WROT2_SW_RST_DONE_ENG_EVENT 316
+#define CMDQ_EVENT_MML1_MDP_WROT1_SW_RST_DONE_ENG_EVENT 317
+#define CMDQ_EVENT_MML1_MDP_WROT0_SW_RST_DONE_ENG_EVENT 318
+#define CMDQ_EVENT_MML1_MDP_RROT0_SW_RST_DONE_ENG_EVENT 319
+#define CMDQ_EVENT_MML1_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 320
+#define CMDQ_EVENT_MML1_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 321
+#define CMDQ_EVENT_MML1_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 322
+#define CMDQ_EVENT_MML1_MDP_MERGE0_SW_RST_DONE_ENG_EVENT 323
+#define CMDQ_EVENT_MML1_DISP_MUTEX0_TIMEOUT_ENG_EVENT 324
+#define CMDQ_EVENT_MML1_DISP_MUTEX0_GET_RLZ_ENG_EVENT 325
+
+#define CMDQ_EVENT_OVL0_STREAM_SOF0 326
+#define CMDQ_EVENT_OVL0_STREAM_SOF1 327
+#define CMDQ_EVENT_OVL0_STREAM_SOF2 328
+#define CMDQ_EVENT_OVL0_STREAM_SOF3 329
+#define CMDQ_EVENT_OVL0_STREAM_SOF4 330
+#define CMDQ_EVENT_OVL0_STREAM_SOF5 331
+#define CMDQ_EVENT_OVL0_STREAM_SOF6 332
+#define CMDQ_EVENT_OVL0_STREAM_SOF7 333
+#define CMDQ_EVENT_OVL0_STREAM_SOF8 334
+#define CMDQ_EVENT_OVL0_STREAM_SOF9 335
+#define CMDQ_EVENT_OVL0_STREAM_SOF10 336
+#define CMDQ_EVENT_OVL0_STREAM_SOF11 337
+#define CMDQ_EVENT_OVL0_STREAM_SOF12 338
+#define CMDQ_EVENT_OVL0_STREAM_SOF13 339
+#define CMDQ_EVENT_OVL0_STREAM_SOF14 340
+#define CMDQ_EVENT_OVL0_STREAM_SOF15 341
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL0 342
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL1 343
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL2 344
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL3 345
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL4 346
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL5 347
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL6 348
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL7 349
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL8 350
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL9 351
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL10 352
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL11 353
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL12 354
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL13 355
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL14 356
+#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL15 357
+#define CMDQ_EVENT_OVL0_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 358
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_TIMEOUT_ENG_EVENT 359
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 360
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT1 361
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT2 362
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT3 363
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT4 364
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT5 365
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT6 366
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT7 367
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT8 368
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT9 369
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT10 370
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT11 371
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT12 372
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT13 373
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT14 374
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT15 375
+#define CMDQ_EVENT_OVL0_OVL_MUTEX0_GET_RELEASE_ENG_EVENT 376
+#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 377
+#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 378
+#define CMDQ_EVENT_OVL0_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT 379
+#define CMDQ_EVENT_OVL0_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT 380
+#define CMDQ_EVENT_OVL0_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT 381
+#define CMDQ_EVENT_OVL0_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT 382
+#define CMDQ_EVENT_OVL0_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT 383
+#define CMDQ_EVENT_OVL0_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT 384
+#define CMDQ_EVENT_OVL0_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT 385
+#define CMDQ_EVENT_OVL0_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT 386
+#define CMDQ_EVENT_OVL0_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT 387
+#define CMDQ_EVENT_OVL0_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT 388
+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 389
+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT 390
+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 391
+#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT 392
+#define CMDQ_EVENT_OVL0_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT 393
+#define CMDQ_EVENT_OVL1_STREAM_SOF0 394
+#define CMDQ_EVENT_OVL1_STREAM_SOF1 395
+#define CMDQ_EVENT_OVL1_STREAM_SOF2 396
+#define CMDQ_EVENT_OVL1_STREAM_SOF3 397
+#define CMDQ_EVENT_OVL1_STREAM_SOF4 398
+#define CMDQ_EVENT_OVL1_STREAM_SOF5 399
+#define CMDQ_EVENT_OVL1_STREAM_SOF6 400
+#define CMDQ_EVENT_OVL1_STREAM_SOF7 401
+#define CMDQ_EVENT_OVL1_STREAM_SOF8 402
+#define CMDQ_EVENT_OVL1_STREAM_SOF9 403
+#define CMDQ_EVENT_OVL1_STREAM_SOF10 404
+#define CMDQ_EVENT_OVL1_STREAM_SOF11 405
+#define CMDQ_EVENT_OVL1_STREAM_SOF12 406
+#define CMDQ_EVENT_OVL1_STREAM_SOF13 407
+#define CMDQ_EVENT_OVL1_STREAM_SOF14 408
+#define CMDQ_EVENT_OVL1_STREAM_SOF15 409
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL0 410
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL1 411
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL2 412
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL3 413
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL4 414
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL5 415
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL6 416
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL7 417
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL8 418
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL9 419
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL10 420
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL11 421
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL12 422
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL13 423
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL14 424
+#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL15 425
+#define CMDQ_EVENT_OVL1_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 426
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_TIMEOUT_ENG_EVENT 427
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 428
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT1 429
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT2 430
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT3 431
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT4 432
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT5 433
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT6 434
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT7 435
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT8 436
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT9 437
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT10 438
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT11 439
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT12 440
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT13 441
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT14 442
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT15 443
+#define CMDQ_EVENT_OVL1_OVL_MUTEX0_GET_RELEASE_ENG_EVENT 444
+#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 445
+#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 446
+#define CMDQ_EVENT_OVL1_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT 447
+#define CMDQ_EVENT_OVL1_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT 448
+#define CMDQ_EVENT_OVL1_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT 449
+#define CMDQ_EVENT_OVL1_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT 450
+#define CMDQ_EVENT_OVL1_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT 451
+#define CMDQ_EVENT_OVL1_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT 452
+#define CMDQ_EVENT_OVL1_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT 453
+#define CMDQ_EVENT_OVL1_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT 454
+#define CMDQ_EVENT_OVL1_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT 455
+#define CMDQ_EVENT_OVL1_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT 456
+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 457
+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT 458
+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 459
+#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT 460
+#define CMDQ_EVENT_OVL1_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT 461
+
+#define CMDQ_EVENT_DPC_DT_DONE0 462
+#define CMDQ_EVENT_DPC_DT_DONE1 463
+#define CMDQ_EVENT_DPC_DT_DONE2_0_MERGE 464
+#define CMDQ_EVENT_DPC_DT_DONE2_1_MERGE 465
+#define CMDQ_EVENT_DPC_DT_DONE2_2_MERGE 466
+#define CMDQ_EVENT_DPC_DT_DONE2_3_MERGE 467
+#define CMDQ_EVENT_DPC_DT_DONE3 468
+#define CMDQ_EVENT_DPC_DT_DONE4_MERGE 469
+#define CMDQ_EVENT_DPC_DT_DONE5 470
+#define CMDQ_EVENT_DPC_DT_DONE6_0_MERGE 471
+#define CMDQ_EVENT_DPC_DT_DONE6_1_MERGE 472
+#define CMDQ_EVENT_DPC_DT_DONE6_2_MERGE 473
+#define CMDQ_EVENT_DPC_DT_DONE6_3_MERGE 474
+#define CMDQ_EVENT_DPC_DT_DONE7 475
+#define CMDQ_EVENT_DPC_DT_DONE32_MERGE 476
+#define CMDQ_EVENT_DPC_DT_DONE33 477
+#define CMDQ_EVENT_DPC_DT_DONE34_0 478
+#define CMDQ_EVENT_DPC_DT_DONE35 479
+#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_ON_BEFORE_OFF 480
+#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_PRETE_BEFORE_ON 481
+#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_ON_BEFORE_OFF 482
+#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_PRETE_BEFORE_ON 483
+#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_ON_BEFORE_OFF 484
+#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_PRETE_BEFORE_ON 485
+#define CMDQ_EVENT_DPC_DISP_SW_CONFIG_WHEN_MTCMOS_OFF 486
+#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_ON_BEFORE_OFF 487
+#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_PRETE_BEFORE_ON 488
+#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_ON_BEFORE_OFF 489
+#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_PRETE_BEFORE_ON 490
+#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_ON_BEFORE_OFF 491
+#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_PRETE_BEFORE_ON 492
+#define CMDQ_EVENT_DPC_MML_SW_CONFIG_WHEN_MTCMOS_OFF 493
+#define CMDQ_EVENT_DPTX_DPTX_EVENT0 494
+#define CMDQ_EVENT_DPTX_DPTX_EVENT1 495
+#define CMDQ_EVENT_DPTX_DPTX_EVENT2 496
+#define CMDQ_EVENT_DPTX_DPTX_EVENT3 497
+#define CMDQ_EVENT_EDPTX_EDPTX_EVENT0 498
+#define CMDQ_EVENT_EDPTX_EDPTX_EVENT1 499
+
+#define CMDQ_EVENT_DSI0_TE_I_DSI0_TE_I 898
+#define CMDQ_EVENT_DSI1_TE_I_DSI1_TE_I 899
+#define CMDQ_EVENT_DSI2_TE_I_DSI2_TE_I 900
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_0 901
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_1 902
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_2 903
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_3 904
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_4 905
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_5 906
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_6 907
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_7 908
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_8 909
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_9 910
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_10 911
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_11 912
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_12 913
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_13 914
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_14 915
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_15 916
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_16 917
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_17 918
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_18 919
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_19 920
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_20 921
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_21 922
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_22 923
+#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK_23 924
+#define CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX_0 925
+#define CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX_1 926
+#define CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P1_0 927
+#define CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P1_1 928
+#define CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX_0 929
+#define CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX_1 930
+#define CMDQ_EVENT_DSI3_TE_I_DSI3_TE_I 931
+#define CMDQ_EVENT_SPI0_FINISH_EVENT_DSI4_TE_I 932
+#define CMDQ_EVENT_SPI0_EVENT_EVENT_DSI5_TE_I 933
+
+/* GCE-M hardware events */
+#define CMDQ_EVENT_VENC3_VENC_RESERVED 0
+#define CMDQ_EVENT_VENC3_VENC_FRAME_DONE 1
+#define CMDQ_EVENT_VENC3_VENC_PAUSE_DONE 2
+#define CMDQ_EVENT_VENC3_JPGENC_DONE 3
+#define CMDQ_EVENT_VENC3_VENC_MB_DONE 4
+#define CMDQ_EVENT_VENC3_VENC_128BYTE_DONE 5
+#define CMDQ_EVENT_VENC3_JPGDEC_DONE 6
+#define CMDQ_EVENT_VENC3_JPGDEC_C1_DONE 7
+#define CMDQ_EVENT_VENC3_JPGDEC_INSUFF_DONE 8
+#define CMDQ_EVENT_VENC3_JPGDEC_C1_INSUFF_DONE 9
+#define CMDQ_EVENT_VENC3_WP_2ND_STAGE_DONE 10
+#define CMDQ_EVENT_VENC3_WP_3RD_STAGE_DONE 11
+#define CMDQ_EVENT_VENC3_PPS_HEADER_DONE 12
+#define CMDQ_EVENT_VENC3_SPS_HEADER_DONE 13
+#define CMDQ_EVENT_VENC3_VPS_HEADER_DONE 14
+#define CMDQ_EVENT_VENC3_VENC_SLICE_DONE 15
+#define CMDQ_EVENT_VENC3_VENC_SOC_SLICE_DONE 16
+#define CMDQ_EVENT_VENC3_VENC_SOC_FRAME_DONE 17
+
+#define CMDQ_EVENT_VENC2_VENC_FRAME_DONE 33
+#define CMDQ_EVENT_VENC2_VENC_PAUSE_DONE 34
+#define CMDQ_EVENT_VENC2_JPGENC_DONE 35
+#define CMDQ_EVENT_VENC2_VENC_MB_DONE 36
+#define CMDQ_EVENT_VENC2_VENC_128BYTE_DONE 37
+#define CMDQ_EVENT_VENC2_JPGDEC_DONE 38
+#define CMDQ_EVENT_VENC2_JPGDEC_C1_DONE 39
+#define CMDQ_EVENT_VENC2_JPGDEC_INSUFF_DONE 40
+#define CMDQ_EVENT_VENC2_JPGDEC_C1_INSUFF_DONE 41
+#define CMDQ_EVENT_VENC2_WP_2ND_STAGE_DONE 42
+#define CMDQ_EVENT_VENC2_WP_3RD_STAGE_DONE 43
+#define CMDQ_EVENT_VENC2_PPS_HEADER_DONE 44
+#define CMDQ_EVENT_VENC2_SPS_HEADER_DONE 45
+#define CMDQ_EVENT_VENC2_VPS_HEADER_DONE 46
+#define CMDQ_EVENT_VENC2_VENC_SLICE_DONE 47
+#define CMDQ_EVENT_VENC2_VENC_SOC_SLICE_DONE 48
+#define CMDQ_EVENT_VENC2_VENC_SOC_FRAME_DONE 49
+
+#define CMDQ_EVENT_VENC1_VENC_FRAME_DONE 65
+#define CMDQ_EVENT_VENC1_VENC_PAUSE_DONE 66
+#define CMDQ_EVENT_VENC1_JPGENC_DONE 67
+#define CMDQ_EVENT_VENC1_VENC_MB_DONE 68
+#define CMDQ_EVENT_VENC1_VENC_128BYTE_DONE 69
+#define CMDQ_EVENT_VENC1_JPGDEC_DONE 70
+#define CMDQ_EVENT_VENC1_JPGDEC_C1_DONE 71
+#define CMDQ_EVENT_VENC1_JPGDEC_INSUFF_DONE 72
+#define CMDQ_EVENT_VENC1_JPGDEC_C1_INSUFF_DONE 73
+#define CMDQ_EVENT_VENC1_WP_2ND_STAGE_DONE 74
+#define CMDQ_EVENT_VENC1_WP_3RD_STAGE_DONE 75
+#define CMDQ_EVENT_VENC1_PPS_HEADER_DONE 76
+#define CMDQ_EVENT_VENC1_SPS_HEADER_DONE 77
+#define CMDQ_EVENT_VENC1_VPS_HEADER_DONE 78
+#define CMDQ_EVENT_VENC1_VENC_SLICE_DONE 79
+#define CMDQ_EVENT_VENC1_VENC_SOC_SLICE_DONE 80
+#define CMDQ_EVENT_VENC1_VENC_SOC_FRAME_DONE 81
+
+#define CMDQ_EVENT_VDEC1_VDEC_LINE_CNT_INT 192
+#define CMDQ_EVENT_VDEC1_VDEC_INT 193
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_2 194
+#define CMDQ_EVENT_VDEC1_VDEC_DEC_ERR 195
+#define CMDQ_EVENT_VDEC1_VDEC_BUSY_OVERFLOW 196
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_5 197
+#define CMDQ_EVENT_VDEC1_VDEC_INI_FETCH_RDY 198
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_7 199
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_8 200
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_9 201
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_10 202
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_11 203
+
+#define CMDQ_EVENT_VDEC1_VDEC_GCE_CNT_OP_THR 207
+
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_32 224
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_INT 225
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_34 226
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_DEC_ERR 227
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_BUSY_OVERFLOW 228
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_37 229
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_INI_FETCH_RDY 230
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_39 231
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_40 232
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_41 233
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_42 234
+#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_43 235
+
+#define CMDQ_EVENT_VDEC1_VDEC_LAT_GCE_CNT_OP_THR 239
+
+#define CMDQ_EVENT_IMG_IMG_EVENT_0 256
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0 257
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_1 258
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_2 259
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_3 260
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_4 261
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_5 262
+#define CMDQ_EVENT_IMG_TRAW0_DMA_ERR_EVENT 263
+#define CMDQ_EVENT_IMG_TRAW0_DUMMY_0 264
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0 265
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_1 266
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_2 267
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_3 268
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_4 269
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_5 270
+#define CMDQ_EVENT_IMG_TRAW1_DMA_ERR_EVENT 271
+#define CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT 272
+#define CMDQ_EVENT_IMG_ADLWR0_TILE_DONE_EVENT 273
+#define CMDQ_EVENT_IMG_ADLWR1_TILE_DONE_EVENT 274
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 275
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_MMG_DONE 276
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_0 277
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_1 278
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_2 279
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_3 280
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_4 281
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_5 282
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_6 283
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_7 284
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_8 285
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_9 286
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_10 287
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_11 288
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_12 289
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_13 290
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_14 291
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_15 292
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_16 293
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_17 294
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_18 295
+#define CMDQ_EVENT_IMG_QOF_ACK_EVENT_19 296
+#define CMDQ_EVENT_IMG_QOF_ON_EVENT_0 297
+#define CMDQ_EVENT_IMG_QOF_ON_EVENT_1 298
+#define CMDQ_EVENT_IMG_QOF_ON_EVENT_2 299
+#define CMDQ_EVENT_IMG_QOF_ON_EVENT_3 300
+#define CMDQ_EVENT_IMG_QOF_ON_EVENT_4 301
+#define CMDQ_EVENT_IMG_QOF_OFF_EVENT_0 302
+#define CMDQ_EVENT_IMG_QOF_OFF_EVENT_1 303
+#define CMDQ_EVENT_IMG_QOF_OFF_EVENT_2 304
+#define CMDQ_EVENT_IMG_QOF_OFF_EVENT_3 305
+#define CMDQ_EVENT_IMG_QOF_OFF_EVENT_4 306
+#define CMDQ_EVENT_IMG_QOF_SAVE_EVENT_0 307
+#define CMDQ_EVENT_IMG_QOF_SAVE_EVENT_1 308
+#define CMDQ_EVENT_IMG_QOF_SAVE_EVENT_2 309
+#define CMDQ_EVENT_IMG_QOF_SAVE_EVENT_3 310
+#define CMDQ_EVENT_IMG_QOF_SAVE_EVENT_4 311
+#define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT_0 312
+#define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT_1 313
+#define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT_2 314
+#define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT_3 315
+#define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT_4 316
+
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_0 317
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_1 318
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_2 319
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_3 320
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_4 321
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_5 322
+#define CMDQ_EVENT_IMG_DIP_DMA_ERR_EVENT 323
+#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR_EVENT 324
+#define CMDQ_EVENT_IMG_DIP_DUMMY_0 325
+
+#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 326
+#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 327
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_0 328
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_1 329
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_2 330
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_3 331
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_4 332
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_5 333
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_0 334
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_1 335
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_2 336
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_3 337
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_4 338
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_5 339
+#define CMDQ_EVENT_IMG_PQA_DMA_ERR_EVENT 340
+#define CMDQ_EVENT_IMG_WPE0_DUMMY_0 341
+#define CMDQ_EVENT_IMG_WPE0_DUMMY_1 342
+#define CMDQ_EVENT_IMG_WPE0_DUMMY_2 343
+#define CMDQ_EVENT_IMG_OMC_TNR_GCE_FRAME_DONE 344
+#define CMDQ_EVENT_IMG_OMC_TNR_DONE_SYNC_OUT 345
+#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2_0 346
+#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2_1 347
+#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2_2 348
+#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2_3 349
+#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2_4 350
+#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2_5 351
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_0 352
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_1 353
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_2 354
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_3 355
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_4 356
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_5 357
+#define CMDQ_EVENT_IMG_PQB_DMA_ERR_EVENT 358
+#define CMDQ_EVENT_IMG_WPE1_DUMMY_0 359
+#define CMDQ_EVENT_IMG_WPE1_DUMMY_1 360
+#define CMDQ_EVENT_IMG_WPE1_DUMMY_2 361
+#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 362
+#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 363
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_0 364
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_1 365
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_2 366
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_3 367
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_4 368
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_5 369
+#define CMDQ_EVENT_IMG_OMC_LITE_GCE_FRAME_DONE 370
+#define CMDQ_EVENT_IMG_OMC_LITE_DONE_SYNC_OUT 371
+#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2_0 372
+#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2_1 373
+#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2_2 374
+#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2_3 375
+#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2_4 376
+#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2_5 377
+#define CMDQ_EVENT_IMG_WPE2_DUMMY_0 378
+#define CMDQ_EVENT_IMG_WPE2_DUMMY_1 379
+#define CMDQ_EVENT_IMG_WPE2_DUMMY_2 380
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE 381
+#define CMDQ_EVENT_IMG_IMG_EVENT_126 382
+#define CMDQ_EVENT_IMG_IMG_EVENT_127 383
+
+#define CMDQ_EVENT_CAM_CAM_EVENT_0 384
+#define CMDQ_EVENT_CAM_CAM_SUBA_SW_PASS1_DONE 385
+#define CMDQ_EVENT_CAM_CAM_SUBB_SW_PASS1_DONE 386
+#define CMDQ_EVENT_CAM_CAM_SUBC_SW_PASS1_DONE 387
+#define CMDQ_EVENT_CAM_CAM_SUBA_TFMR_PASS1_DONE 388
+#define CMDQ_EVENT_CAM_CAM_SUBB_TFMR_PASS1_DONE 389
+#define CMDQ_EVENT_CAM_CAM_SUBC_TFMR_PASS1_DONE 390
+#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE_0 391
+#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE_1 392
+#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE_2 393
+#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE_3 394
+#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE_0 395
+#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE_1 396
+#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE_2 397
+#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE_3 398
+#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE_0 399
+#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE_1 400
+#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE_2 401
+#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE_3 402
+#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE_0 403
+#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE_1 404
+#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE_2 405
+#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE_3 406
+#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE_0 407
+#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE_1 408
+#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE_2 409
+#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE_3 410
+#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE_0 411
+#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE_1 412
+#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE_2 413
+#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE_3 414
+#define CMDQ_EVENT_CAM_MRAW0_SW_PASS1_DONE 415
+#define CMDQ_EVENT_CAM_MRAW1_SW_PASS1_DONE 416
+#define CMDQ_EVENT_CAM_MRAW2_SW_PASS1_DONE 417
+#define CMDQ_EVENT_CAM_MRAW3_SW_PASS1_DONE 418
+#define CMDQ_EVENT_CAM_UISP_SW_PASS1_DONE 419
+#define CMDQ_EVENT_CAM_TG_MRAW0_OUT_SOF 420
+#define CMDQ_EVENT_CAM_TG_MRAW1_OUT_SOF 421
+#define CMDQ_EVENT_CAM_TG_MRAW2_OUT_SOF 422
+#define CMDQ_EVENT_CAM_TG_MRAW3_OUT_SOF 423
+#define CMDQ_EVENT_CAM_PDA0_IRQO_EVENT_DONE_D1 424
+#define CMDQ_EVENT_CAM_PDA1_IRQO_EVENT_DONE_D1 425
+
+#define CMDQ_EVENT_CAM_DPE_DVP_CMQ_EVENT 426
+#define CMDQ_EVENT_CAM_DPE_DVS_CMQ_EVENT 427
+#define CMDQ_EVENT_CAM_DPE_DVFG_CMQ_EVENT 428
+#define CMDQ_EVENT_CAM_CAM_EVENT_45 429
+#define CMDQ_EVENT_CAM_CAM_EVENT_46 430
+#define CMDQ_EVENT_CAM_CAM_EVENT_47 431
+#define CMDQ_EVENT_CAM_CAM_EVENT_48 432
+#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT1 433
+#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT2 434
+#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT3 435
+#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT4 436
+#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT1 437
+#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT2 438
+#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT3 439
+#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT4 440
+#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT1 441
+#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT2 442
+#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT3 443
+#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT4 444
+#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBA 445
+#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBB 446
+#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBC 447
+#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBA 448
+#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBB 449
+#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBC 450
+#define CMDQ_EVENT_CAM_RAW_SEL_SOF_UISP 451
+#define CMDQ_EVENT_CAM_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 452
+#define CMDQ_EVENT_CAM_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 453
+#define CMDQ_EVENT_CAM_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 454
+#define CMDQ_EVENT_CAM_CAM_EVENT_71 455
+#define CMDQ_EVENT_CAM_ADL_WR_FRAME_DONE 456
+#define CMDQ_EVENT_CAM_ADL_RD_FRAME_DONE 457
+#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_ON_EVENT 458
+#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_ON_EVENT 459
+#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_ON_EVENT 460
+#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_OFF_EVENT 461
+#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_OFF_EVENT 462
+#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_OFF_EVENT 463
+#define CMDQ_EVENT_CAM_QOF_RAWA_SAVE_EVENT 464
+#define CMDQ_EVENT_CAM_QOF_RAWB_SAVE_EVENT 465
+#define CMDQ_EVENT_CAM_QOF_RAWC_SAVE_EVENT 466
+#define CMDQ_EVENT_CAM_QOF_RAWA_RESTORE_EVENT 467
+#define CMDQ_EVENT_CAM_QOF_RAWB_RESTORE_EVENT 468
+#define CMDQ_EVENT_CAM_QOF_RAWC_RESTORE_EVENT 469
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_0 470
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_1 471
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_2 472
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_3 473
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_4 474
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_5 475
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_6 476
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_7 477
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_8 478
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_9 479
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_10 480
+#define CMDQ_EVENT_CAM_QOF_CAM_EVENT_11 481
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_0 482
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_1 483
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_2 484
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_3 485
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_4 486
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_5 487
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_6 488
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_7 489
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_8 490
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_9 491
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_10 492
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_11 493
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_12 494
+#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT_13 495
+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_NON_SEC_IRQ 496
+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_SEC_IRQ 497
+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_VM_IRQ 498
+#define CMDQ_EVENT_CAM_CCU0_TO_GCE_EXCH_VM_IRQ 499
+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_NON_SEC_IRQ 500
+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_SEC_IRQ 501
+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_VM_IRQ 502
+#define CMDQ_EVENT_CAM_CCU1_TO_GCE_EXCH_VM_IRQ 503
+#define CMDQ_EVENT_CAM_I2C_CH2_EVENT_0 504
+#define CMDQ_EVENT_CAM_I2C_CH2_EVENT_1 505
+#define CMDQ_EVENT_CAM_I2C_CH2_EVENT_2 506
+#define CMDQ_EVENT_CAM_I2C_CH2_EVENT_3 507
+#define CMDQ_EVENT_CAM_I2C_CH2_EVENT_4 508
+#define CMDQ_EVENT_CAM_CAM_EVENT_125 509
+#define CMDQ_EVENT_CAM_CAM_EVENT_126 510
+#define CMDQ_EVENT_CAM_CAM_EVENT_127 511
+
+#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MMSRAM_COMM_SMIASSER 898
+#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MDP_COMM_SMIASSER 899
+#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_DISP_COMM_SMIASSER 900
+
+#define CMDQ_MAX_HW_EVENT 512
+/* End of hardware event and begin of software token */
+
+/*
+ * CMDQ software tokens:
+ * The following are GCE software tokens, which can be used by clients
+ * event to operate API.
+ */
+
+/* Begin of GCE-D software token */
+/* MML software tokens */
+#define CMDQ_SYNC_TOKEN_MML_BUFA 630
+#define CMDQ_SYNC_TOKEN_MML_BUFB 631
+#define CMDQ_SYNC_TOKEN_MML_BUF_NEXT 632
+#define CMDQ_SYNC_TOKEN_MML_IR_MML_READY 633
+#define CMDQ_SYNC_TOKEN_MML_IR_DISP_READY 634
+#define CMDQ_SYNC_TOKEN_MML_MML_STOP 635
+#define CMDQ_SYNC_TOKEN_MML_PIPE0 636
+#define CMDQ_SYNC_TOKEN_MML_PIPE1 637
+#define CMDQ_SYNC_TOKEN_MML_PIPE1_NEXT 638
+#define CMDQ_SYNC_TOKEN_MML_APU_START 639
+
+/* Config thread notify trigger thread */
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640
+/* Trigger thread notify config thread */
+#define CMDQ_SYNC_TOKEN_STREAM_EOF 641
+/* Block Trigger thread until the ESD check finishes */
+#define CMDQ_SYNC_TOKEN_ESD_EOF 642
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643
+/* Check CABC setup finish */
+#define CMDQ_SYNC_TOKEN_CABC_EOF 644
+
+/* VFP period token for Msync */
+#define CMDQ_SYNC_TOKEN_VFP_PERIOD 645
+/* Software sync token for dual display */
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1 694
+#define CMDQ_SYNC_TOKEN_STREAM_EOF_1 695
+#define CMDQ_SYNC_TOKEN_ESD_EOF_1 696
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_1 697
+#define CMDQ_SYNC_TOKEN_CABC_EOF_1 698
+
+/*
+ * GPR access tokens (for HW register backup)
+ * There are 15 32-bit GPR, form 3 GPR as a set
+ * (64-bit for address, 32-bit for value)
+ */
+#define CMDQ_SYNC_TOKEN_GPR_SET_0 700
+#define CMDQ_SYNC_TOKEN_GPR_SET_1 701
+#define CMDQ_SYNC_TOKEN_GPR_SET_2 702
+#define CMDQ_SYNC_TOKEN_GPR_SET_3 703
+#define CMDQ_SYNC_TOKEN_GPR_SET_4 704
+
+#define CMDQ_SYNC_TOKEN_TE_0 705
+#define CMDQ_SYNC_TOKEN_PREFETCH_TE_0 706
+#define CMDQ_SYNC_TOKEN_VIDLE_POWER_ON 707
+#define CMDQ_SYNC_TOKEN_CHECK_TRIGGER_MERGE 708
+
+/* Resource lock event to control resource in GCE thread */
+#define CMDQ_SYNC_RESOURCE_WROT0 710
+#define CMDQ_SYNC_RESOURCE_WROT1 711
+
+/* Hardware TRACE software token */
+#define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT 712
+#define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK 713
+
+/* Software sync token for dual display */
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3 714
+#define CMDQ_SYNC_TOKEN_STREAM_EOF_3 715
+#define CMDQ_SYNC_TOKEN_ESD_EOF_3 716
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_3 717
+#define CMDQ_SYNC_TOKEN_CABC_EOF_3 718
+/* End of GCE-D software token */
+
+/* Begin of GCE-M software token */
+/* IMGSYS_POOL */
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1 514
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2 515
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3 516
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4 517
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5 518
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6 519
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7 520
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8 521
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9 522
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10 523
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11 524
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12 525
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13 526
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14 527
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15 528
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16 529
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17 530
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18 531
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19 532
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20 533
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_21 534
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_22 535
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_23 536
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_24 537
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_25 538
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_26 539
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_27 540
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_28 541
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_29 542
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_30 543
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_31 544
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_32 545
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_33 546
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_34 547
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_35 548
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_36 549
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_37 550
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_38 551
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_39 552
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_40 553
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_41 554
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_42 555
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_43 556
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_44 557
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_45 558
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_46 559
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_47 560
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_48 561
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_49 562
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_50 563
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_51 564
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_52 565
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_53 566
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_54 567
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_55 568
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_56 569
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_57 570
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_58 571
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_59 572
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_60 573
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_61 574
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_62 575
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_63 576
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_64 577
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_65 578
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_66 579
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_67 580
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_68 581
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_69 582
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_70 583
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_71 584
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_72 585
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_73 586
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_74 587
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_75 588
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_76 589
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_77 590
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_78 591
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_79 592
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_80 593
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_81 594
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_82 595
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_83 596
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_84 597
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_85 598
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_86 599
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_87 600
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_88 601
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_89 602
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_90 603
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_91 604
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_92 605
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_93 606
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_94 607
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_95 608
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_96 609
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_97 610
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_98 611
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_99 612
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_100 613
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_101 614
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_102 615
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_103 616
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_104 617
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_105 618
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_106 619
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_107 620
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_108 621
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_109 622
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_110 623
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_111 624
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_112 625
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_113 626
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_114 627
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_115 628
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_116 629
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_117 630
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_118 631
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_119 632
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_120 633
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_121 634
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_122 635
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_123 636
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_124 637
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_125 638
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_126 639
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_127 640
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_128 641
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_129 642
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_130 643
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_131 644
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_132 645
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_133 646
+
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_134 694
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_135 695
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_136 696
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_137 697
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_138 698
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_139 699
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_140 700
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_141 701
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_142 702
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_143 703
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_144 704
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_145 705
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_146 706
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_147 707
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_148 708
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_149 709
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_150 710
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_151 711
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_152 714
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_153 715
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_154 716
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_155 717
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_156 718
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_157 719
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_158 720
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_159 721
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_160 722
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_161 723
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_162 724
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_163 725
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_164 726
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_165 727
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_166 728
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_167 729
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_168 730
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_169 731
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_170 732
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_171 733
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_172 734
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_173 735
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_174 736
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_175 737
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_176 738
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_177 739
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_178 740
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_179 741
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_180 742
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_181 743
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_182 744
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_183 745
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_184 746
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_185 747
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_186 748
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_187 749
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_188 750
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_189 751
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_190 752
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_191 753
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_192 754
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_193 755
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_194 756
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_195 757
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_196 758
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_197 759
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_198 760
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_199 761
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_200 762
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_201 763
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_202 764
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_203 765
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_204 766
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_205 767
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_206 784
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_207 785
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_208 786
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_209 787
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_210 788
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_211 789
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_212 790
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_213 791
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_214 792
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_215 793
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_216 794
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_217 795
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_218 796
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_219 797
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_220 798
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_221 799
+
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_222 833
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_223 834
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_224 835
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_225 836
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_226 837
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_227 838
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_228 839
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_229 840
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_230 841
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_231 842
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_232 843
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_233 844
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_234 845
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_235 846
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_236 847
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_237 848
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_238 849
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_239 850
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_240 851
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_241 852
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_242 853
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_243 854
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_244 855
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_245 856
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_246 857
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_247 858
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_248 859
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_249 860
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_250 861
+
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_251 901
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_252 902
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_253 903
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_254 904
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_255 905
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_256 906
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_257 907
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_258 908
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_259 909
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_260 910
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_261 911
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_262 912
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_263 913
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_264 914
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_265 915
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_266 916
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_267 917
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_268 918
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_269 919
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_270 920
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_271 921
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_272 922
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_273 923
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_274 924
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_275 925
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_276 926
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_277 927
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_278 928
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_279 929
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_280 930
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_281 931
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_282 932
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_283 933
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_284 934
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_285 935
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_286 936
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_287 937
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_288 938
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_289 939
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_290 940
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_291 941
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_292 942
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_293 943
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_294 944
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_295 945
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_296 946
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_297 947
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_298 948
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_299 949
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_300 950
+
+/* ISP software token */
+#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 665
+#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_TNR 666
+#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 667
+#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 668
+#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 669
+#define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 670
+#define CMDQ_SYNC_TOKEN_IMGSYS_DIP 671
+#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 672
+#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 673
+#define CMDQ_SYNC_TOKEN_IPESYS_ME 674
+#define CMDQ_SYNC_TOKEN_APUSYS_APU 675
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 676
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 677
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 678
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 679
+#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_LITE 680
+
+/* IMG software token for QoS */
+#define CMDQ_SYNC_TOKEN_IMGSYS_QOS_LOCK 800
+/* IMG software token for Qof */
+#define CMDQ_SYNC_TOKEN_DIP_POWER_CTRL 862
+#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_ON 863
+#define CMDQ_SYNC_TOKEN_DIP_PWR_ON 864
+#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_OFF 865
+#define CMDQ_SYNC_TOKEN_DIP_PWR_OFF 866
+#define CMDQ_SYNC_TOKEN_DIP_PWR_HAND_SHAKE 867
+
+#define CMDQ_SYNC_TOKEN_TRAW_POWER_CTRL 868
+#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_ON 869
+#define CMDQ_SYNC_TOKEN_TRAW_PWR_ON 870
+#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_OFF 871
+#define CMDQ_SYNC_TOKEN_TRAW_PWR_OFF 872
+#define CMDQ_SYNC_TOKEN_TRAW_PWR_HAND_SHAKE 873
+/* End of GCE-M software token */
+
+/* Begin of common software token */
+
+/*
+ * Notify normal CMDQ there are some secure task done
+ * MUST NOT CHANGE, this token sync with secure world
+ */
+#define CMDQ_SYNC_SECURE_THR_EOF 647
+
+/* CMDQ use software token */
+#define CMDQ_SYNC_TOKEN_USER_0 649
+#define CMDQ_SYNC_TOKEN_USER_1 650
+#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651
+#define CMDQ_SYNC_TOKEN_TPR_LOCK 652
+
+/* TZMP software token */
+#define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT 653
+#define CMDQ_SYNC_TOKEN_TZMP_DISP_SET 654
+#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 655
+#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 656
+#define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT 657
+#define CMDQ_SYNC_TOKEN_TZMP_AIE_SET 658
+#define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT 659
+#define CMDQ_SYNC_TOKEN_TZMP_ADL_SET 660
+
+/* PREBUILT software token */
+#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 682
+#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 685
+#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 688
+#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 691
+#define CMDQ_SYNC_TOKEN_DISP_VA_START 692
+#define CMDQ_SYNC_TOKEN_DISP_VA_END 693
+
+/* Event for GPR timer, used in sleep and poll with timeout */
+#define CMDQ_TOKEN_GPR_TIMER_R0 994
+#define CMDQ_TOKEN_GPR_TIMER_R1 995
+#define CMDQ_TOKEN_GPR_TIMER_R2 996
+#define CMDQ_TOKEN_GPR_TIMER_R3 997
+#define CMDQ_TOKEN_GPR_TIMER_R4 998
+#define CMDQ_TOKEN_GPR_TIMER_R5 999
+#define CMDQ_TOKEN_GPR_TIMER_R6 1000
+#define CMDQ_TOKEN_GPR_TIMER_R7 1001
+#define CMDQ_TOKEN_GPR_TIMER_R8 1002
+#define CMDQ_TOKEN_GPR_TIMER_R9 1003
+#define CMDQ_TOKEN_GPR_TIMER_R10 1004
+#define CMDQ_TOKEN_GPR_TIMER_R11 1005
+#define CMDQ_TOKEN_GPR_TIMER_R12 1006
+#define CMDQ_TOKEN_GPR_TIMER_R13 1007
+#define CMDQ_TOKEN_GPR_TIMER_R14 1008
+#define CMDQ_TOKEN_GPR_TIMER_R15 1009
+
+#define CMDQ_EVENT_MAX 0x3ff
+/* End of common software token */
+/* CMDQ software tokens END */
+
+#endif
+
--
2.43.0On Thu, Nov 21, 2024 at 12:25:55PM +0800, Jason-JH.Lin wrote: > Add the Global Command Engine (GCE) header file to define the GCE > thread priority, GCE subsys ID, GCE events, and various constants > for MT8196. NAK, various constants are not bindings. > > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> > --- > .../dt-bindings/mailbox/mediatek,mt8196-gce.h | 1449 +++++++++++++++++ > 1 file changed, 1449 insertions(+) > create mode 100755 include/dt-bindings/mailbox/mediatek,mt8196-gce.h Please run scripts/checkpatch.pl and fix reported warnings. Then please run 'scripts/checkpatch.pl --strict' and (probably) fix more warnings. Some warnings can be ignored, especially from --strict run, but the code here looks like it needs a fix. Feel free to get in touch if the warning is not clear. This goes with the binding. Best regards, Krzysztof
Hi Krzysztof, Thanks for the reviews. On Thu, 2024-11-21 at 09:42 +0100, Krzysztof Kozlowski wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > On Thu, Nov 21, 2024 at 12:25:55PM +0800, Jason-JH.Lin wrote: > > Add the Global Command Engine (GCE) header file to define the GCE > > thread priority, GCE subsys ID, GCE events, and various constants > > for MT8196. > > NAK, various constants are not bindings. > OK, I'll drop the constants. > > > > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> > > --- > > .../dt-bindings/mailbox/mediatek,mt8196-gce.h | 1449 > > +++++++++++++++++ > > 1 file changed, 1449 insertions(+) > > create mode 100755 include/dt-bindings/mailbox/mediatek,mt8196- > > gce.h > > Please run scripts/checkpatch.pl and fix reported warnings. Then > please > run 'scripts/checkpatch.pl --strict' and (probably) fix more > warnings. > Some warnings can be ignored, especially from --strict run, but the > code > here looks like it needs a fix. Feel free to get in touch if the > warning > is not clear. > > This goes with the binding. > I thought I have done that, but I found a whitespace warning at #1328 now. I'll fix that at the next version. Thanks for the reminder. Regards, Jason-JH.Lin > Best regards, > Krzysztof >
On 21/11/2024 11:51, Jason-JH Lin (林睿祥) wrote: >>> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> >>> --- >>> .../dt-bindings/mailbox/mediatek,mt8196-gce.h | 1449 >>> +++++++++++++++++ >>> 1 file changed, 1449 insertions(+) >>> create mode 100755 include/dt-bindings/mailbox/mediatek,mt8196- >>> gce.h >> >> Please run scripts/checkpatch.pl and fix reported warnings. Then >> please >> run 'scripts/checkpatch.pl --strict' and (probably) fix more >> warnings. >> Some warnings can be ignored, especially from --strict run, but the >> code >> here looks like it needs a fix. Feel free to get in touch if the >> warning >> is not clear. >> >> This goes with the binding. >> > > I thought I have done that, but I found a whitespace warning at #1328 > now. I'll fix that at the next version. > Thanks for the reminder. There are multiple errors, including executable permission. I don't believe you run checkpatch. Best regards, Krzysztof
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