From: "Friday Yang" <friday.yang@mediatek.com>
To support SMI clamp and reset operation in genpd callback, add
SMI LARB reset controller in the bindings. Add index in
mt8188-resets.h to query the reset signal in the SMI reset
control driver.
Signed-off-by: Friday Yang <friday.yang@mediatek.com>
---
.../bindings/reset/mediatek,smi-reset.yaml | 53 +++++++++++++++++++
include/dt-bindings/reset/mt8188-resets.h | 11 ++++
2 files changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
new file mode 100644
index 000000000000..77a6197a9846
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek SMI Reset Controller
+
+maintainers:
+ - Friday Yang <friday.yang@mediatek.com>
+
+description: |
+ This reset controller node is used to perform reset management
+ of SMI larbs on MediaTek platform. It is used to implement various
+ reset functions required when SMI larbs apply clamp operation.
+
+ For list of all valid reset indices see
+ <dt-bindings/reset/mt8188-resets.h> for MT8188.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-smi-reset
+
+ "#reset-cells":
+ const: 1
+ description:
+ The cell should be the device ID. SMI reset controller driver could
+ query the reset signal of each SMI larb by device ID.
+
+ mediatek,larb-rst:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of each subsys clock controller. SMI larbs are located in
+ these subsys. SMI needs to parse the node of each subsys clock
+ controller to get the register address, and then apply the reset
+ operation.
+
+required:
+ - compatible
+ - "#reset-cells"
+ - mediatek,larb-rst
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller {
+ compatible = "mediatek,mt8188-smi-reset";
+ #reset-cells = <1>;
+ mediatek,larb-rst = <&imgsys1_dip_top>;
+ };
diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index 5a58c54e7d20..387a4beac688 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -113,4 +113,15 @@
#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52
#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53
+#define MT8188_SMI_RST_LARB10 0
+#define MT8188_SMI_RST_LARB11A 1
+#define MT8188_SMI_RST_LARB11C 2
+#define MT8188_SMI_RST_LARB12 3
+#define MT8188_SMI_RST_LARB11B 4
+#define MT8188_SMI_RST_LARB15 5
+#define MT8188_SMI_RST_LARB16B 6
+#define MT8188_SMI_RST_LARB17B 7
+#define MT8188_SMI_RST_LARB16A 8
+#define MT8188_SMI_RST_LARB17A 9
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.46.0On Wed, Nov 20, 2024 at 02:32:55PM +0800, Friday Yang wrote: > From: "Friday Yang" <friday.yang@mediatek.com> > > To support SMI clamp and reset operation in genpd callback, add > SMI LARB reset controller in the bindings. Add index in > mt8188-resets.h to query the reset signal in the SMI reset > control driver. > > Signed-off-by: Friday Yang <friday.yang@mediatek.com> > --- > .../bindings/reset/mediatek,smi-reset.yaml | 53 +++++++++++++++++++ > include/dt-bindings/reset/mt8188-resets.h | 11 ++++ > 2 files changed, 64 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml > > diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml > new file mode 100644 > index 000000000000..77a6197a9846 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml > @@ -0,0 +1,53 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2024 MediaTek Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek SMI Reset Controller > + > +maintainers: > + - Friday Yang <friday.yang@mediatek.com> > + > +description: | > + This reset controller node is used to perform reset management > + of SMI larbs on MediaTek platform. It is used to implement various > + reset functions required when SMI larbs apply clamp operation. > + > + For list of all valid reset indices see > + <dt-bindings/reset/mt8188-resets.h> for MT8188. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8188-smi-reset > + Where is MMIO space? > + "#reset-cells": > + const: 1 > + description: > + The cell should be the device ID. SMI reset controller driver could > + query the reset signal of each SMI larb by device ID. > + > + mediatek,larb-rst: > + $ref: /schemas/types.yaml#/definitions/phandle Ah, here it is? No, that is not how you access device MMIO. Use reg property for this. That's a gross misrepresentation of hardware. Best regards, Krzysztof
Hi, Friday:
On Wed, 2024-11-20 at 14:32 +0800, Friday Yang wrote:
> From: "Friday Yang" <friday.yang@mediatek.com>
>
> To support SMI clamp and reset operation in genpd callback, add
> SMI LARB reset controller in the bindings. Add index in
> mt8188-resets.h to query the reset signal in the SMI reset
> control driver.
>
> Signed-off-by: Friday Yang <friday.yang@mediatek.com>
> ---
> .../bindings/reset/mediatek,smi-reset.yaml | 53 +++++++++++++++++++
> include/dt-bindings/reset/mt8188-resets.h | 11 ++++
> 2 files changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
>
> diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> new file mode 100644
> index 000000000000..77a6197a9846
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml*__;Iw!!CTRNKA9wMg0ARbw!gdXglQJh0-FDFibSUah2aNWBcdxp70BO2OQgeO0iq660S3-nixB7L2xJnKDsMlilUnctbSbP9KNv_Ot8e2aDow$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!gdXglQJh0-FDFibSUah2aNWBcdxp70BO2OQgeO0iq660S3-nixB7L2xJnKDsMlilUnctbSbP9KNv_OvQ-6vNSA$
> +
> +title: MediaTek SMI Reset Controller
> +
> +maintainers:
> + - Friday Yang <friday.yang@mediatek.com>
> +
> +description: |
> + This reset controller node is used to perform reset management
> + of SMI larbs on MediaTek platform. It is used to implement various
> + reset functions required when SMI larbs apply clamp operation.
> +
> + For list of all valid reset indices see
> + <dt-bindings/reset/mt8188-resets.h> for MT8188.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt8188-smi-reset
> +
> + "#reset-cells":
> + const: 1
> + description:
> + The cell should be the device ID. SMI reset controller driver could
> + query the reset signal of each SMI larb by device ID.
> +
> + mediatek,larb-rst:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle of each subsys clock controller. SMI larbs are located in
> + these subsys. SMI needs to parse the node of each subsys clock
> + controller to get the register address, and then apply the reset
> + operation.
> +
> +required:
> + - compatible
> + - "#reset-cells"
> + - mediatek,larb-rst
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + reset-controller {
> + compatible = "mediatek,mt8188-smi-reset";
> + #reset-cells = <1>;
> + mediatek,larb-rst = <&imgsys1_dip_top>;
It seems that imgsys1-dip-top device [1] is a syscon (system controller) device not a pure clock controller.
It is similar to mmsys device [2].
mmsys driver is in [3].
Because clock maintainer insist on placing clock control part in clock driver folder,
so the clock control sub driver is in [4].
The reset control is in mmsys main driver, and main driver would probe the clock sub driver.
Refer to mmsys device to refine imgsys1-dip-top device.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml?h=v6.12#n37
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml?h=v6.12
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=v6.12
[4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8188-vdo0.c?h=v6.12
Regards,
CK
> + };
> diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
> index 5a58c54e7d20..387a4beac688 100644
> --- a/include/dt-bindings/reset/mt8188-resets.h
> +++ b/include/dt-bindings/reset/mt8188-resets.h
> @@ -113,4 +113,15 @@
> #define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52
> #define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53
>
> +#define MT8188_SMI_RST_LARB10 0
> +#define MT8188_SMI_RST_LARB11A 1
> +#define MT8188_SMI_RST_LARB11C 2
> +#define MT8188_SMI_RST_LARB12 3
> +#define MT8188_SMI_RST_LARB11B 4
> +#define MT8188_SMI_RST_LARB15 5
> +#define MT8188_SMI_RST_LARB16B 6
> +#define MT8188_SMI_RST_LARB17B 7
> +#define MT8188_SMI_RST_LARB16A 8
> +#define MT8188_SMI_RST_LARB17A 9
> +
> #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
> --
> 2.46.0
>
>
Il 20/11/24 07:32, Friday Yang ha scritto:
> From: "Friday Yang" <friday.yang@mediatek.com>
>
> To support SMI clamp and reset operation in genpd callback, add
> SMI LARB reset controller in the bindings. Add index in
> mt8188-resets.h to query the reset signal in the SMI reset
> control driver.
>
> Signed-off-by: Friday Yang <friday.yang@mediatek.com>
> ---
> .../bindings/reset/mediatek,smi-reset.yaml | 53 +++++++++++++++++++
> include/dt-bindings/reset/mt8188-resets.h | 11 ++++
> 2 files changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
>
> diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> new file mode 100644
> index 000000000000..77a6197a9846
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek SMI Reset Controller
> +
> +maintainers:
> + - Friday Yang <friday.yang@mediatek.com>
> +
> +description: |
> + This reset controller node is used to perform reset management
> + of SMI larbs on MediaTek platform. It is used to implement various
> + reset functions required when SMI larbs apply clamp operation.
> +
> + For list of all valid reset indices see
> + <dt-bindings/reset/mt8188-resets.h> for MT8188.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt8188-smi-reset
> +
> + "#reset-cells":
> + const: 1
> + description:
> + The cell should be the device ID. SMI reset controller driver could
> + query the reset signal of each SMI larb by device ID.
> +
> + mediatek,larb-rst:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle of each subsys clock controller. SMI larbs are located in
> + these subsys. SMI needs to parse the node of each subsys clock
> + controller to get the register address, and then apply the reset
> + operation.
> +
> +required:
> + - compatible
> + - "#reset-cells"
> + - mediatek,larb-rst
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + reset-controller {
> + compatible = "mediatek,mt8188-smi-reset";
> + #reset-cells = <1>;
> + mediatek,larb-rst = <&imgsys1_dip_top>;
I don't understand why would you be unable to add the SMI resets to the already
currently supported reset code in the clock-controller driver itself, like done
with literally all of the other clock controllers.
Please clarify.
Regards,
Angelo
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