qcom: llcc/edac: Correct interrupt enable register configuration

[PATCH] qcom: llcc/edac: Correct interrupt enable register configuration

Posted by Komal Bajaj 1 year, 2 months ago

The previous implementation incorrectly configured the cmn_interrupt_2_enable
register for interrupt handling. Using cmn_interrupt_2_enable to configure Tag,
Data RAM ECC interrupts would lead to issues like double handling of the
interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured
for interrupts which needs to be handled by EL3.

EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to
configure Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable.

Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs")
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
 drivers/edac/qcom_edac.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
index a9a8ba067007..0fd7a777fe7d 100644
--- a/drivers/edac/qcom_edac.c
+++ b/drivers/edac/qcom_edac.c
@@ -95,7 +95,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b
 	 * Configure interrupt enable registers such that Tag, Data RAM related
 	 * interrupts are propagated to interrupt controller for servicing
 	 */
-	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
+	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,
 				 TRP0_INTERRUPT_ENABLE,
 				 TRP0_INTERRUPT_ENABLE);
 	if (ret)
@@ -113,7 +113,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b
 	if (ret)
 		return ret;

-	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
+	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,
 				 DRP0_INTERRUPT_ENABLE,
 				 DRP0_INTERRUPT_ENABLE);
 	if (ret)
--
2.46.0

Re: [PATCH] qcom: llcc/edac: Correct interrupt enable register configuration

Posted by Manivannan Sadhasivam 11 months, 4 weeks ago

On Tue, Nov 19, 2024 at 12:16:08PM +0530, Komal Bajaj wrote:
> The previous implementation incorrectly configured the cmn_interrupt_2_enable
> register for interrupt handling. Using cmn_interrupt_2_enable to configure Tag,
> Data RAM ECC interrupts would lead to issues like double handling of the
> interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured
> for interrupts which needs to be handled by EL3.
> 
> EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to
> configure Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable.
> 

Cc: stable@vger.kernel.org

> Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs")
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
>  drivers/edac/qcom_edac.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> index a9a8ba067007..0fd7a777fe7d 100644
> --- a/drivers/edac/qcom_edac.c
> +++ b/drivers/edac/qcom_edac.c
> @@ -95,7 +95,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b
>  	 * Configure interrupt enable registers such that Tag, Data RAM related
>  	 * interrupts are propagated to interrupt controller for servicing
>  	 */
> -	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
> +	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,
>  				 TRP0_INTERRUPT_ENABLE,
>  				 TRP0_INTERRUPT_ENABLE);
>  	if (ret)
> @@ -113,7 +113,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b
>  	if (ret)
>  		return ret;
> 
> -	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
> +	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,
>  				 DRP0_INTERRUPT_ENABLE,
>  				 DRP0_INTERRUPT_ENABLE);
>  	if (ret)
> --
> 2.46.0
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH] qcom: llcc/edac: Correct interrupt enable register configuration

Posted by Borislav Petkov 11 months, 4 weeks ago

On Fri, Feb 14, 2025 at 06:48:40PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Nov 19, 2024 at 12:16:08PM +0530, Komal Bajaj wrote:
> > The previous implementation incorrectly configured the cmn_interrupt_2_enable
> > register for interrupt handling. Using cmn_interrupt_2_enable to configure Tag,
> > Data RAM ECC interrupts would lead to issues like double handling of the
> > interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured
> > for interrupts which needs to be handled by EL3.
> > 
> > EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to
> > configure Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable.
> > 
> 
> Cc: stable@vger.kernel.org
> 
> > Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs")
> > Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH] qcom: llcc/edac: Correct interrupt enable register configuration

Posted by Dmitry Baryshkov 1 year, 2 months ago

On Tue, Nov 19, 2024 at 12:16:08PM +0530, Komal Bajaj wrote:
> The previous implementation incorrectly configured the cmn_interrupt_2_enable
> register for interrupt handling. Using cmn_interrupt_2_enable to configure Tag,
> Data RAM ECC interrupts would lead to issues like double handling of the
> interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured
> for interrupts which needs to be handled by EL3.

This reads as if it was possible to write EL3-related register from EL1.
Is it true?

> 
> EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to
> configure Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable.
> 
> Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs")
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
>  drivers/edac/qcom_edac.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> index a9a8ba067007..0fd7a777fe7d 100644
> --- a/drivers/edac/qcom_edac.c
> +++ b/drivers/edac/qcom_edac.c
> @@ -95,7 +95,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b
>  	 * Configure interrupt enable registers such that Tag, Data RAM related
>  	 * interrupts are propagated to interrupt controller for servicing
>  	 */
> -	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
> +	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,
>  				 TRP0_INTERRUPT_ENABLE,
>  				 TRP0_INTERRUPT_ENABLE);
>  	if (ret)
> @@ -113,7 +113,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b
>  	if (ret)
>  		return ret;
> 
> -	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
> +	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,
>  				 DRP0_INTERRUPT_ENABLE,
>  				 DRP0_INTERRUPT_ENABLE);
>  	if (ret)
> --
> 2.46.0
> 

-- 
With best wishes
Dmitry

Re: [PATCH] qcom: llcc/edac: Correct interrupt enable register configuration

Posted by Komal Bajaj 1 year, 2 months ago

On 11/20/2024 5:29 PM, Dmitry Baryshkov wrote:
> On Tue, Nov 19, 2024 at 12:16:08PM +0530, Komal Bajaj wrote:
>> The previous implementation incorrectly configured the cmn_interrupt_2_enable
>> register for interrupt handling. Using cmn_interrupt_2_enable to configure Tag,
>> Data RAM ECC interrupts would lead to issues like double handling of the
>> interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured
>> for interrupts which needs to be handled by EL3.
> This reads as if it was possible to write EL3-related register from EL1.
> Is it true?


Both EL1 and EL3 can access the LLCC "cmn_interrupt_2_enable" register, 
but configuring the register from both
EL1 & EL3 shouldn't be done as the register is meant to be configured 
from EL3. There was a bug in HPG which was
fixed recently on not to configure the register from EL1.

Thanks
Komal


>> EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to
>> configure Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable.
>>
>> Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs")
>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>> ---
>>   drivers/edac/qcom_edac.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
>> index a9a8ba067007..0fd7a777fe7d 100644
>> --- a/drivers/edac/qcom_edac.c
>> +++ b/drivers/edac/qcom_edac.c
>> @@ -95,7 +95,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b
>>   	 * Configure interrupt enable registers such that Tag, Data RAM related
>>   	 * interrupts are propagated to interrupt controller for servicing
>>   	 */
>> -	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
>> +	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,
>>   				 TRP0_INTERRUPT_ENABLE,
>>   				 TRP0_INTERRUPT_ENABLE);
>>   	if (ret)
>> @@ -113,7 +113,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b
>>   	if (ret)
>>   		return ret;
>>
>> -	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
>> +	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,
>>   				 DRP0_INTERRUPT_ENABLE,
>>   				 DRP0_INTERRUPT_ENABLE);
>>   	if (ret)
>> --
>> 2.46.0
>>

Re: [PATCH] qcom: llcc/edac: Correct interrupt enable register configuration

Posted by Komal Bajaj 11 months, 4 weeks ago



On 12/5/2024 3:59 PM, Komal Bajaj wrote:
>
> On 11/20/2024 5:29 PM, Dmitry Baryshkov wrote:
>> On Tue, Nov 19, 2024 at 12:16:08PM +0530, Komal Bajaj wrote:
>>> The previous implementation incorrectly configured the 
>>> cmn_interrupt_2_enable
>>> register for interrupt handling. Using cmn_interrupt_2_enable to 
>>> configure Tag,
>>> Data RAM ECC interrupts would lead to issues like double handling of 
>>> the
>>> interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be 
>>> configured
>>> for interrupts which needs to be handled by EL3.
>> This reads as if it was possible to write EL3-related register from EL1.
>> Is it true?
>
>
> Both EL1 and EL3 can access the LLCC "cmn_interrupt_2_enable" 
> register, but configuring the register from both
> EL1 & EL3 shouldn't be done as the register is meant to be configured 
> from EL3. There was a bug in HPG which was
> fixed recently on not to configure the register from EL1.
>
> Thanks
> Komal

Hi Dmitry,
Does this answer your query, or is there anything else you are looking for?

Thanks
Komal

>
>
>>> EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to
>>> configure Tag, Data RAM ECC interrupts instead of 
>>> cmn_interrupt_2_enable.
>>>
>>> Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for 
>>> QCOM SoCs")
>>> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>>> ---
>>>   drivers/edac/qcom_edac.c | 4 ++--
>>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
>>> index a9a8ba067007..0fd7a777fe7d 100644
>>> --- a/drivers/edac/qcom_edac.c
>>> +++ b/drivers/edac/qcom_edac.c
>>> @@ -95,7 +95,7 @@ static int qcom_llcc_core_setup(struct 
>>> llcc_drv_data *drv, struct regmap *llcc_b
>>>        * Configure interrupt enable registers such that Tag, Data 
>>> RAM related
>>>        * interrupts are propagated to interrupt controller for 
>>> servicing
>>>        */
>>> -    ret = regmap_update_bits(llcc_bcast_regmap, 
>>> drv->edac_reg_offset->cmn_interrupt_2_enable,
>>> +    ret = regmap_update_bits(llcc_bcast_regmap, 
>>> drv->edac_reg_offset->cmn_interrupt_0_enable,
>>>                    TRP0_INTERRUPT_ENABLE,
>>>                    TRP0_INTERRUPT_ENABLE);
>>>       if (ret)
>>> @@ -113,7 +113,7 @@ static int qcom_llcc_core_setup(struct 
>>> llcc_drv_data *drv, struct regmap *llcc_b
>>>       if (ret)
>>>           return ret;
>>>
>>> -    ret = regmap_update_bits(llcc_bcast_regmap, 
>>> drv->edac_reg_offset->cmn_interrupt_2_enable,
>>> +    ret = regmap_update_bits(llcc_bcast_regmap, 
>>> drv->edac_reg_offset->cmn_interrupt_0_enable,
>>>                    DRP0_INTERRUPT_ENABLE,
>>>                    DRP0_INTERRUPT_ENABLE);
>>>       if (ret)
>>> -- 
>>> 2.46.0
>>>