AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
max-speed is made a required property, and it breaks DT ABI but driver
implementation ensures backward compatibility and assumes 1G when this
property is absent.
Modify existing bindings description for 2.5G MAC.
Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
.../bindings/net/xlnx,axi-ethernet.yaml | 44 +++++++++++++++++--
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
index fb02e579463c..69e84e2e2b63 100644
--- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
+++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
@@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem
description: |
Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
provides connectivity to an external ethernet PHY supporting different
- interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
+ interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also includes two
segments of memory for buffering TX and RX, as well as the capability of
offloading TX/RX checksum calculation off the processor.
+ AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G speed.
+
Management configuration is done through the AXI interface, while payload is
sent and received through means of an AXI DMA controller. This driver
includes the DMA driver code, so this driver is incompatible with AXI DMA
@@ -62,6 +64,7 @@ properties:
- rgmii
- sgmii
- 1000base-x
+ - 2500base-x
xlnx,phy-type:
description:
@@ -118,9 +121,9 @@ properties:
type: object
pcs-handle:
- description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
- modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
- and "phy-handle" should point to an external PHY if exists.
+ description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-x/
+ 2500base-x modes, where "pcs-handle" should be used to point to the
+ PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists.
maxItems: 1
dmas:
@@ -137,12 +140,17 @@ properties:
minItems: 2
maxItems: 32
+ max-speed:
+ description:
+ Indicates max MAC rate. 1G and 2.5G MACs of AXI 1G/2.5G IP are distinguished using it.
+
required:
- compatible
- interrupts
- reg
- xlnx,rxmem
- phy-handle
+ - max-speed
allOf:
- $ref: /schemas/net/ethernet-controller.yaml#
@@ -164,6 +172,7 @@ examples:
xlnx,rxmem = <0x800>;
xlnx,txcsum = <0x2>;
phy-handle = <&phy0>;
+ max-speed = <1000>;
mdio {
#address-cells = <1>;
@@ -188,6 +197,7 @@ examples:
xlnx,txcsum = <0x2>;
phy-handle = <&phy1>;
axistream-connected = <&dma>;
+ max-speed = <1000>;
mdio {
#address-cells = <1>;
@@ -198,3 +208,29 @@ examples:
};
};
};
+
+# AXI 2.5G MAC
+ - |
+ axi_ethernet_eth2: ethernet@a4000000 {
+ compatible = "xlnx,axi-ethernet-1.00.a";
+ interrupts = <0>;
+ clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
+ clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
+ phy-mode = "2500base-x";
+ reg = <0x40000000 0x40000>;
+ xlnx,rxcsum = <0x2>;
+ xlnx,rxmem = <0x800>;
+ xlnx,txcsum = <0x2>;
+ phy-handle = <&phy1>;
+ axistream-connected = <&dma>;
+ max-speed = <2500>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@1 {
+ device_type = "ethernet-phy";
+ reg = <1>;
+ };
+ };
+ };
--
2.25.1On 18/11/2024 09:18, Suraj Gupta wrote: > AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed" > property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP. > max-speed is made a required property, and it breaks DT ABI but driver > implementation ensures backward compatibility and assumes 1G when this > property is absent. > Modify existing bindings description for 2.5G MAC. > > Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com> Please start using b4. This thread is a mess. Do not attach (thread) your patchsets to some other threads (unrelated or older versions). This buries them deep in the mailbox and might interfere with applying entire sets. <form letter> Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. Tools like b4 or scripts/get_maintainer.pl provide you proper list of people, so fix your workflow. Tools might also fail if you work on some ancient tree (don't, instead use mainline) or work on fork of kernel (don't, instead use mainline). Just use b4 and everything should be fine, although remember about `b4 prep --auto-to-cc` if you added new patches to the patchset. You missed at least devicetree list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time. Please kindly resend and include all necessary To/Cc entries. </form letter> Best regards, Krzysztof
Hello, On Mon, 18 Nov 2024 13:48:21 +0530 Suraj Gupta <suraj.gupta2@amd.com> wrote: > AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed" > property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP. > max-speed is made a required property, and it breaks DT ABI but driver > implementation ensures backward compatibility and assumes 1G when this > property is absent. > Modify existing bindings description for 2.5G MAC. That may be a silly question, but as this is another version of the IP that behaves differently than the 1G version, could you use instead a dedicated compatible string for the 2.5G variant ? As the current one is : compatible = "xlnx,axi-ethernet-1.00.a"; it seems to already contain some version information. But I might also be missing something :) Best regards, Maxime
On 11/18/24 10:54, Maxime Chevallier wrote: > Hello, > > On Mon, 18 Nov 2024 13:48:21 +0530 > Suraj Gupta <suraj.gupta2@amd.com> wrote: > >> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed" >> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP. >> max-speed is made a required property, and it breaks DT ABI but driver >> implementation ensures backward compatibility and assumes 1G when this >> property is absent. >> Modify existing bindings description for 2.5G MAC. > > That may be a silly question, but as this is another version of the IP > that behaves differently than the 1G version, could you use instead a > dedicated compatible string for the 2.5G variant ? > > As the current one is : > > compatible = "xlnx,axi-ethernet-1.00.a"; > > it seems to already contain some version information. > > But I might also be missing something :) As it happens, this is not another version of the same IP but a different configuration. It's just that no one has bothered to add 2.5G support yet. And to my understanding, the device tree should not contain any info that can be reliably detected from the hardware. --Sean
On Mon, Nov 18, 2024 at 10:57:45AM -0500, Sean Anderson wrote: > On 11/18/24 10:54, Maxime Chevallier wrote: > > Hello, > > > > On Mon, 18 Nov 2024 13:48:21 +0530 > > Suraj Gupta <suraj.gupta2@amd.com> wrote: > > > >> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed" > >> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP. > >> max-speed is made a required property, and it breaks DT ABI but driver > >> implementation ensures backward compatibility and assumes 1G when this > >> property is absent. > >> Modify existing bindings description for 2.5G MAC. > > > > That may be a silly question, but as this is another version of the IP > > that behaves differently than the 1G version, could you use instead a > > dedicated compatible string for the 2.5G variant ? > > > > As the current one is : > > > > compatible = "xlnx,axi-ethernet-1.00.a"; > > > > it seems to already contain some version information. > > > > But I might also be missing something :) > > As it happens, this is not another version of the same IP but a > different configuration. It's just that no one has bothered to add 2.5G > support yet. Do you mean 2.5G is a synthesis option? Or are you saying it has always been able to do 2.5G, but nobody has added the needed code? This is a pretty unusual use of max-speed, so i would like to fully understand why it is being used before allowing it. Andrew
On 11/18/24 03:18, Suraj Gupta wrote:
> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> max-speed is made a required property, and it breaks DT ABI but driver
> implementation ensures backward compatibility and assumes 1G when this
> property is absent.
> Modify existing bindings description for 2.5G MAC.
>
> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> ---
> .../bindings/net/xlnx,axi-ethernet.yaml | 44 +++++++++++++++++--
> 1 file changed, 40 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> index fb02e579463c..69e84e2e2b63 100644
> --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> @@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem
> description: |
> Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
> provides connectivity to an external ethernet PHY supporting different
> - interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
> + interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also includes two
> segments of memory for buffering TX and RX, as well as the capability of
> offloading TX/RX checksum calculation off the processor.
>
> + AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G speed.
> +
> Management configuration is done through the AXI interface, while payload is
> sent and received through means of an AXI DMA controller. This driver
> includes the DMA driver code, so this driver is incompatible with AXI DMA
> @@ -62,6 +64,7 @@ properties:
> - rgmii
> - sgmii
> - 1000base-x
> + - 2500base-x
>
> xlnx,phy-type:
> description:
> @@ -118,9 +121,9 @@ properties:
> type: object
>
> pcs-handle:
> - description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
> - modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
> - and "phy-handle" should point to an external PHY if exists.
> + description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-x/
> + 2500base-x modes, where "pcs-handle" should be used to point to the
> + PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists.
> maxItems: 1
>
> dmas:
> @@ -137,12 +140,17 @@ properties:
> minItems: 2
> maxItems: 32
>
> + max-speed:
> + description:
> + Indicates max MAC rate. 1G and 2.5G MACs of AXI 1G/2.5G IP are distinguished using it.
> +
Can't you read this from the TEMAC ability register?
--Sean
> required:
> - compatible
> - interrupts
> - reg
> - xlnx,rxmem
> - phy-handle
> + - max-speed
>
> allOf:
> - $ref: /schemas/net/ethernet-controller.yaml#
> @@ -164,6 +172,7 @@ examples:
> xlnx,rxmem = <0x800>;
> xlnx,txcsum = <0x2>;
> phy-handle = <&phy0>;
> + max-speed = <1000>;
>
> mdio {
> #address-cells = <1>;
> @@ -188,6 +197,7 @@ examples:
> xlnx,txcsum = <0x2>;
> phy-handle = <&phy1>;
> axistream-connected = <&dma>;
> + max-speed = <1000>;
>
> mdio {
> #address-cells = <1>;
> @@ -198,3 +208,29 @@ examples:
> };
> };
> };
> +
> +# AXI 2.5G MAC
> + - |
> + axi_ethernet_eth2: ethernet@a4000000 {
> + compatible = "xlnx,axi-ethernet-1.00.a";
> + interrupts = <0>;
> + clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
> + clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
> + phy-mode = "2500base-x";
> + reg = <0x40000000 0x40000>;
> + xlnx,rxcsum = <0x2>;
> + xlnx,rxmem = <0x800>;
> + xlnx,txcsum = <0x2>;
> + phy-handle = <&phy1>;
> + axistream-connected = <&dma>;
> + max-speed = <2500>;
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy2: ethernet-phy@1 {
> + device_type = "ethernet-phy";
> + reg = <1>;
> + };
> + };
> + };
© 2016 - 2024 Red Hat, Inc.