From: Vignesh Raghavendra <vigneshr@ti.com>
Add the initial infrastructure needed for the AM62L. All of which can be
found in the Technical Reference Manual (TRM) located here:
https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
---
Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++
arch/arm64/boot/dts/ti/Makefile | 3 +
arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 52 ++++++++++++++
arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 33 +++++++++
arch/arm64/boot/dts/ti/k3-am62l.dtsi | 89 ++++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 +
7 files changed, 252 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index 18f155cd06c84..b109e854879cb 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -31,6 +31,12 @@ properties:
- const: phytec,am62a-phycore-som
- const: ti,am62a7
+ - description: K3 AM62L3 SoC and Boards
+ items:
+ - enum:
+ - ti,am62l3-evm
+ - const: ti,am62l3
+
- description: K3 AM62P5 SoC and Boards
items:
- enum:
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index f71360f14f233..6745f779b1e6e 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -32,6 +32,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb
+# Boards with AM62Lx SoCs
+dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm.dtb
+
# Boards with AM62Px SoC
dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi
new file mode 100644
index 0000000000000..bdc6cb26a86d3
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree file for the AM62L main domain peripherals
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
+ */
+
+&cbass_main {
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01840000 0x00 0xc0000>, /* GICR */
+ <0x01 0x00000000 0x00 0x2000>, /* GICC */
+ <0x01 0x00010000 0x00 0x1000>, /* GICH */
+ <0x01 0x00020000 0x00 0x2000>; /* GICV */
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ oc_sram: sram@70800000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x70800000 0x00 0x10000>;
+ ranges = <0x0 0x00 0x70800000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
new file mode 100644
index 0000000000000..070ba71110f0f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree file for the AM62L wakeup domain peripherals
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
+ */
+
+&cbass_wakeup {
+ pmx0: pinctrl@4084000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x4084000 0x00 0x8000>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ #pinctrl-cells = <1>;
+ bootph-all;
+ };
+
+ wkup_conf: bus@43000000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x43000000 0x00 0x20000>;
+ ranges = <0x0 0x00 0x43000000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chipid: chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ bootph-all;
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/ti/k3-am62l.dtsi b/arch/arm64/boot/dts/ti/k3-am62l.dtsi
new file mode 100644
index 0000000000000..43da8e52278ce
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62l.dtsi
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree Source for AM62L SoC Family
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Tecnical Reference Manual: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "k3-pinctrl.h"
+
+/ {
+ model = "Texas Instruments K3 AM62L3 SoC";
+ compatible = "ti,am62l3";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@f0000 {
+ compatible = "simple-bus";
+ ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00040000>, /* GTC */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
+ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */
+ <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */
+ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x0bd28000>, /* Second peripheral window */
+ <0x00 0x30200000 0x00 0x30200000 0x00 0x00400000>, /* DSS */
+ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
+ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00001000>, /* GPMC0 */
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x02000000>, /* DMSS */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */
+ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+ <0x00 0x70800000 0x00 0x70800000 0x00 0x00010000>, /* OCSRAM */
+ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+ /* Wakeup Domain Range */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
+ <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
+ <0x00 0x04201000 0x00 0x04201000 0x00 0x00008000>, /* GPIO */
+ <0x00 0x2b100000 0x00 0x2b000000 0x00 0x00200400>, /* TIMER */
+ <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cbass_wakeup: bus@43000000 {
+ compatible = "simple-bus";
+ ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
+ <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
+ <0x00 0x04201000 0x00 0x04201000 0x00 0x00008000>, /* GPIO */
+ <0x00 0x2b100000 0x00 0x2b000000 0x00 0x00200400>, /* TIMER */
+ <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ bootph-all;
+ };
+ };
+};
+
+/* Now include peripherals for each bus segment */
+#include "k3-am62l-main.dtsi"
+#include "k3-am62l-wakeup.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
new file mode 100644
index 0000000000000..7dfc869fbce08
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree file for the AM62L3 SoC family (Dual Core A53)
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
+ */
+
+/dts-v1/;
+
+#include "k3-am62l.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
index 22b8d73cfd326..56abfe1790bee 100644
--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
+++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
@@ -47,6 +47,8 @@
#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM62LX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
--
2.46.0On 18/11/2024 06:34, Bryan Brattlof wrote: > From: Vignesh Raghavendra <vigneshr@ti.com> > > Add the initial infrastructure needed for the AM62L. All of which can be > found in the Technical Reference Manual (TRM) located here: > > https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > Signed-off-by: Bryan Brattlof <bb@ti.com> > --- > Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++ Please run scripts/checkpatch.pl and fix reported warnings. Then please run `scripts/checkpatch.pl --strict` and (probably) fix more warnings. Some warnings can be ignored, especially from --strict run, but the code here looks like it needs a fix. Feel free to get in touch if the warning is not clear. Best regards, Krzysztof
On 16/12/2024 09:10, Krzysztof Kozlowski wrote: > On 18/11/2024 06:34, Bryan Brattlof wrote: >> From: Vignesh Raghavendra <vigneshr@ti.com> >> >> Add the initial infrastructure needed for the AM62L. All of which can be >> found in the Technical Reference Manual (TRM) located here: >> >> https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf >> >> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >> Signed-off-by: Bryan Brattlof <bb@ti.com> >> --- >> Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++ > Please run scripts/checkpatch.pl and fix reported warnings. Then please > run `scripts/checkpatch.pl --strict` and (probably) fix more warnings. > Some warnings can be ignored, especially from --strict run, but the code > here looks like it needs a fix. Feel free to get in touch if the warning > is not clear. Apologies for digging this old thread, some other reply bumped it to top of my inbox. Best regards, Krzysztof
On Sun, Nov 17, 2024 at 11:34:07PM -0600, Bryan Brattlof wrote: > From: Vignesh Raghavendra <vigneshr@ti.com> > > Add the initial infrastructure needed for the AM62L. All of which can be > found in the Technical Reference Manual (TRM) located here: > > https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > Signed-off-by: Bryan Brattlof <bb@ti.com> > --- > Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++ > arch/arm64/boot/dts/ti/Makefile | 3 + > arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 52 ++++++++++++++ > arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 33 +++++++++ > arch/arm64/boot/dts/ti/k3-am62l.dtsi | 89 ++++++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 ++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 + > 7 files changed, 252 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml > index 18f155cd06c84..b109e854879cb 100644 > --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml > +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml > @@ -31,6 +31,12 @@ properties: > - const: phytec,am62a-phycore-som > - const: ti,am62a7 > > + - description: K3 AM62L3 SoC and Boards > + items: > + - enum: > + - ti,am62l3-evm > + - const: ti,am62l3 > + can you clarify the differences between AM62L and AM62L3? you have a mix of names in this series. I assume that AM62L is the SOC family / product name, while AM62L3 is a specific part number. Francesco
On December 14, 2024 thus sayeth Francesco Dolcini:
> On Sun, Nov 17, 2024 at 11:34:07PM -0600, Bryan Brattlof wrote:
> > From: Vignesh Raghavendra <vigneshr@ti.com>
> >
> > Add the initial infrastructure needed for the AM62L. All of which can be
> > found in the Technical Reference Manual (TRM) located here:
> >
> > https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
> >
> > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> > Signed-off-by: Bryan Brattlof <bb@ti.com>
> > ---
> > Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++
> > arch/arm64/boot/dts/ti/Makefile | 3 +
> > arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 52 ++++++++++++++
> > arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 33 +++++++++
> > arch/arm64/boot/dts/ti/k3-am62l.dtsi | 89 ++++++++++++++++++++++++
> > arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 ++++++++++++++++++
> > arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 +
> > 7 files changed, 252 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > index 18f155cd06c84..b109e854879cb 100644
> > --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > @@ -31,6 +31,12 @@ properties:
> > - const: phytec,am62a-phycore-som
> > - const: ti,am62a7
> >
> > + - description: K3 AM62L3 SoC and Boards
> > + items:
> > + - enum:
> > + - ti,am62l3-evm
> > + - const: ti,am62l3
> > +
>
> can you clarify the differences between AM62L and AM62L3? you have a mix of names in this series. I assume that
> AM62L is the SOC family / product name, while AM62L3 is a specific
> part number.
>
Absolutely! I found the naming a bit confusing myself.
We (the baseport teams) have kinda coalesced into using less digits as a
way to describe all devices included in the subgroup. So for example AM6
would be all Sitara class MPUs in the K3 generation. AM62L would be all
parts in K3 in the 'lite' derivative. AM62L32 would be all AM62L parts
with display and dual cores.
But I should probably decode everything as these part numbers are really
opaque in my eye if you don't see them every day.
The full orderable part number for this part is the XAM62L32AOGHAANB
'X' is the production status. If you see an 'X' here it just means
it's a pre-production sample that hasn't gone through validation.
Most of the time (outside of TI) this will be blank
'AM' is the prefix which indicates a Sitara class of SoC. The AM68
and AM69 being originally a Jacinto class part kinda makes this more
confusing but back in the day i think it used to stand for ARM
Microprocessors so that's what I've been telling people.
'62' is the generation and family of the part. So this example the 6
indicates the K3 generation of SoCs and the 2 means it's an MPU
family with 2k display or 2k camera support among other things.
'L' is the derivative of the family. This is mostly a marketing
thing to indicate the target market for the SoC:
AM62 (or blank) would be the general base class
AM62A is for the analytics derivative
AM62D is for DSP
AM62P is for Plus
AM62L is for Lite
'3' is the configuration. This really depends on what the business
teams find feasible. Some of the family/derivative combinations
don't make sense to have. For example an AM62L9 which would just be
the base AM62 derivative, so some configurations may not exist.
0 = No Display / No ISP
1 = No Display with ISP
2 = No Display with ISP and Analytics
3 = Display / No ISP
4 = Display / No ISP with Analytics
5 = Display / No ISP with GPU
6 = Display with ISP
7 = Display with ISP and Analytics
8 = Display with ISP and GPU
9 = includes everything
'2' is the core count. AM62L32 would be the dual core option.
The rest of the digits get into stuff we try to do automatically via our
bootloaders so you wont see any mention of them in Linux, but I kinda
wanted to continue decoding this :)
'A' is the silicon revision. A = SR 1.0
'O' is the speed grade. (there is a table somewhere with all the
speed grades we support. The two I know about are.
O = 1.25GHz
E = 833MHz
'G' is the feature set. Because the derivative is 'L' (or lite) we
probably won't have options other than G which is the baseline
'H' is the security & functional safety value
'G' is non secure no functional safety. (like the beagleplay)
'1-9' are dummy key devices with no functional safety
'H-R' are production key HS devices with no function safety
'S-Z' are production key HS devices with function safety
'H-Z' is probably the most common security you will see TI make now.
There are ways (by talking to sales) you can purchase other variants for
special use cases (like aviation) but I think these are all special use
cases with unique regulatory or security issues.
'A' is the temperature rating
'A' = -40C to 105C
'I' = -40C to 125C
'ANB' is the package: 11.9mm x 11.9mm with 0.5 BGA
There can be a total of 18 digits which can vary when decoding the
family (AM65, AM64) but generally this decoding scheme will hold. I only
really see those weird parts with our vertically integrated customers
with their own sales teams.
Sorry for the essay. I went though our catalog one day and had the very
same question you did so I wanted to dump as much as I could.
~Bryan
Am 14.12.24 um 22:56 schrieb Bryan Brattlof: > On December 14, 2024 thus sayeth Francesco Dolcini: >> On Sun, Nov 17, 2024 at 11:34:07PM -0600, Bryan Brattlof wrote: >>> From: Vignesh Raghavendra <vigneshr@ti.com> >>> >>> Add the initial infrastructure needed for the AM62L. All of which can be >>> found in the Technical Reference Manual (TRM) located here: >>> >>> https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf >>> >>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >>> Signed-off-by: Bryan Brattlof <bb@ti.com> >>> --- >>> Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++ >>> arch/arm64/boot/dts/ti/Makefile | 3 + >>> arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 52 ++++++++++++++ >>> arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 33 +++++++++ >>> arch/arm64/boot/dts/ti/k3-am62l.dtsi | 89 ++++++++++++++++++++++++ >>> arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 ++++++++++++++++++ >>> arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 + >>> 7 files changed, 252 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml >>> index 18f155cd06c84..b109e854879cb 100644 >>> --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml >>> +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml >>> @@ -31,6 +31,12 @@ properties: >>> - const: phytec,am62a-phycore-som >>> - const: ti,am62a7 >>> >>> + - description: K3 AM62L3 SoC and Boards >>> + items: >>> + - enum: >>> + - ti,am62l3-evm >>> + - const: ti,am62l3 >>> + >> >> can you clarify the differences between AM62L and AM62L3? you have a mix of names in this series. I assume that >> AM62L is the SOC family / product name, while AM62L3 is a specific >> part number. >> > > Absolutely! I found the naming a bit confusing myself. > > We (the baseport teams) have kinda coalesced into using less digits as a > way to describe all devices included in the subgroup. So for example AM6 > would be all Sitara class MPUs in the K3 generation. AM62L would be all > parts in K3 in the 'lite' derivative. AM62L32 would be all AM62L parts > with display and dual cores. > > But I should probably decode everything as these part numbers are really > opaque in my eye if you don't see them every day. > > The full orderable part number for this part is the XAM62L32AOGHAANB > > 'X' is the production status. If you see an 'X' here it just means > it's a pre-production sample that hasn't gone through validation. > Most of the time (outside of TI) this will be blank > > 'AM' is the prefix which indicates a Sitara class of SoC. The AM68 > and AM69 being originally a Jacinto class part kinda makes this more > confusing but back in the day i think it used to stand for ARM > Microprocessors so that's what I've been telling people. > > '62' is the generation and family of the part. So this example the 6 > indicates the K3 generation of SoCs and the 2 means it's an MPU > family with 2k display or 2k camera support among other things. > > 'L' is the derivative of the family. This is mostly a marketing > thing to indicate the target market for the SoC: > > AM62 (or blank) would be the general base class > AM62A is for the analytics derivative > AM62D is for DSP > AM62P is for Plus > AM62L is for Lite > > '3' is the configuration. This really depends on what the business > teams find feasible. Some of the family/derivative combinations > don't make sense to have. For example an AM62L9 which would just be > the base AM62 derivative, so some configurations may not exist. > > 0 = No Display / No ISP > 1 = No Display with ISP > 2 = No Display with ISP and Analytics > 3 = Display / No ISP > 4 = Display / No ISP with Analytics > 5 = Display / No ISP with GPU > 6 = Display with ISP > 7 = Display with ISP and Analytics > 8 = Display with ISP and GPU > 9 = includes everything > > '2' is the core count. AM62L32 would be the dual core option. > > The rest of the digits get into stuff we try to do automatically via our > bootloaders so you wont see any mention of them in Linux, but I kinda > wanted to continue decoding this :) > > 'A' is the silicon revision. A = SR 1.0 > > 'O' is the speed grade. (there is a table somewhere with all the > speed grades we support. The two I know about are. > > O = 1.25GHz > E = 833MHz > > 'G' is the feature set. Because the derivative is 'L' (or lite) we > probably won't have options other than G which is the baseline > > 'H' is the security & functional safety value > > 'G' is non secure no functional safety. (like the beagleplay) > '1-9' are dummy key devices with no functional safety > 'H-R' are production key HS devices with no function safety > 'S-Z' are production key HS devices with function safety > > 'H-Z' is probably the most common security you will see TI make now. > There are ways (by talking to sales) you can purchase other variants for > special use cases (like aviation) but I think these are all special use > cases with unique regulatory or security issues. > > 'A' is the temperature rating > > 'A' = -40C to 105C > 'I' = -40C to 125C > > 'ANB' is the package: 11.9mm x 11.9mm with 0.5 BGA > > There can be a total of 18 digits which can vary when decoding the > family (AM65, AM64) but generally this decoding scheme will hold. I only > really see those weird parts with our vertically integrated customers > with their own sales teams. > > Sorry for the essay. I went though our catalog one day and had the very > same question you did so I wanted to dump as much as I could. Thank you for this write up! Will save this mail for future reference. > > ~Bryan >
Hello Bryan, On Sat, Dec 14, 2024 at 03:56:24PM -0600, Bryan Brattlof wrote: > On December 14, 2024 thus sayeth Francesco Dolcini: > > On Sun, Nov 17, 2024 at 11:34:07PM -0600, Bryan Brattlof wrote: > > > From: Vignesh Raghavendra <vigneshr@ti.com> > > > > > > Add the initial infrastructure needed for the AM62L. All of which can be > > > found in the Technical Reference Manual (TRM) located here: > > > > > > https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf > > > > > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > > > Signed-off-by: Bryan Brattlof <bb@ti.com> > > > --- > > > Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++ > > > arch/arm64/boot/dts/ti/Makefile | 3 + > > > arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 52 ++++++++++++++ > > > arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 33 +++++++++ > > > arch/arm64/boot/dts/ti/k3-am62l.dtsi | 89 ++++++++++++++++++++++++ > > > arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 ++++++++++++++++++ > > > arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 + > > > 7 files changed, 252 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml > > > index 18f155cd06c84..b109e854879cb 100644 > > > --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml > > > +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml > > > @@ -31,6 +31,12 @@ properties: > > > - const: phytec,am62a-phycore-som > > > - const: ti,am62a7 > > > > > > + - description: K3 AM62L3 SoC and Boards > > > + items: > > > + - enum: > > > + - ti,am62l3-evm > > > + - const: ti,am62l3 > > > + > > > > can you clarify the differences between AM62L and AM62L3? you have a mix of names in this series. I assume that > > AM62L is the SOC family / product name, while AM62L3 is a specific > > part number. > > > > Absolutely! I found the naming a bit confusing myself. Thanks for the clarification, having ti,am62l3 is consistent with what you did with AM62, in which you have ti,am625. Francesco
On Sun, Nov 17, 2024 at 11:34:07PM -0600, Bryan Brattlof wrote: > From: Vignesh Raghavendra <vigneshr@ti.com> > > Add the initial infrastructure needed for the AM62L. All of which can be > found in the Technical Reference Manual (TRM) located here: > > https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > Signed-off-by: Bryan Brattlof <bb@ti.com> > --- > Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++ Bindings are supposed to be a separate patch. > arch/arm64/boot/dts/ti/Makefile | 3 + > arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 52 ++++++++++++++ > arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 33 +++++++++ > arch/arm64/boot/dts/ti/k3-am62l.dtsi | 89 ++++++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 ++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 + > 7 files changed, 252 insertions(+)
On November 19, 2024 thus sayeth Rob Herring: > On Sun, Nov 17, 2024 at 11:34:07PM -0600, Bryan Brattlof wrote: > > From: Vignesh Raghavendra <vigneshr@ti.com> > > > > Add the initial infrastructure needed for the AM62L. All of which can be > > found in the Technical Reference Manual (TRM) located here: > > > > https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf > > > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > > Signed-off-by: Bryan Brattlof <bb@ti.com> > > --- > > Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++ > > Bindings are supposed to be a separate patch. Ah my bad. I'll split this up in the next version ~Bryan
On 11/17/24 11:34 PM, Bryan Brattlof wrote:
> From: Vignesh Raghavendra <vigneshr@ti.com>
>
> Add the initial infrastructure needed for the AM62L. All of which can be
> found in the Technical Reference Manual (TRM) located here:
>
> https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
We usually use the non-direct links, that way they can be updated
to the latest, so here and everywhere below:
https://www.ti.com/lit/pdf/sprujb4
Also might be good to get the TRM folks to now drop the
"Confidential NDA" watermarks..
>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> ---
> Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++
> arch/arm64/boot/dts/ti/Makefile | 3 +
> arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 52 ++++++++++++++
> arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 33 +++++++++
> arch/arm64/boot/dts/ti/k3-am62l.dtsi | 89 ++++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 ++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 +
> 7 files changed, 252 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> index 18f155cd06c84..b109e854879cb 100644
> --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
> +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> @@ -31,6 +31,12 @@ properties:
> - const: phytec,am62a-phycore-som
> - const: ti,am62a7
>
> + - description: K3 AM62L3 SoC and Boards
> + items:
> + - enum:
> + - ti,am62l3-evm
> + - const: ti,am62l3
> +
> - description: K3 AM62P5 SoC and Boards
> items:
> - enum:
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index f71360f14f233..6745f779b1e6e 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -32,6 +32,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb
>
> +# Boards with AM62Lx SoCs
> +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm.dtb
> +
> # Boards with AM62Px SoC
> dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi
> new file mode 100644
> index 0000000000000..bdc6cb26a86d3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi
> @@ -0,0 +1,52 @@
> +// SPDX-License-Identifier: GPL-2.0-only or MIT
> +/*
> + * Device Tree file for the AM62L main domain peripherals
> + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + *
> + * Technical Reference Manual: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
> + */
> +
> +&cbass_main {
> + gic500: interrupt-controller@1800000 {
> + compatible = "arm,gic-v3";
> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
> + <0x00 0x01840000 0x00 0xc0000>, /* GICR */
> + <0x01 0x00000000 0x00 0x2000>, /* GICC */
> + <0x01 0x00010000 0x00 0x1000>, /* GICH */
> + <0x01 0x00020000 0x00 0x2000>; /* GICV */
> + ranges;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + /*
> + * vcpumntirq:
> + * virtual CPU interface maintenance interrupt
> + */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + gic_its: msi-controller@1820000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x00 0x01820000 0x00 0x10000>;
> + socionext,synquacer-pre-its = <0x1000000 0x400000>;
> + msi-controller;
> + #msi-cells = <1>;
> + };
> + };
> +
> + main_uart0: serial@2800000 {
> + compatible = "ti,am64-uart", "ti,am654-uart";
> + reg = <0x00 0x02800000 0x00 0x100>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + status = "disabled";
> + };
> +
> + oc_sram: sram@70800000 {
> + compatible = "mmio-sram";
> + reg = <0x00 0x70800000 0x00 0x10000>;
> + ranges = <0x0 0x00 0x70800000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
> new file mode 100644
> index 0000000000000..070ba71110f0f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0-only or MIT
> +/*
> + * Device Tree file for the AM62L wakeup domain peripherals
> + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + *
> + * Technical Reference Manual: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
> + */
> +
> +&cbass_wakeup {
> + pmx0: pinctrl@4084000 {
> + compatible = "pinctrl-single";
> + reg = <0x00 0x4084000 0x00 0x8000>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <0xffffffff>;
> + #pinctrl-cells = <1>;
> + bootph-all;
> + };
> +
> + wkup_conf: bus@43000000 {
> + compatible = "simple-bus";
> + reg = <0x00 0x43000000 0x00 0x20000>;
> + ranges = <0x0 0x00 0x43000000 0x20000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chipid: chipid@14 {
> + compatible = "ti,am654-chipid";
> + reg = <0x14 0x4>;
> + bootph-all;
> + };
> + };
> +};
> +
> diff --git a/arch/arm64/boot/dts/ti/k3-am62l.dtsi b/arch/arm64/boot/dts/ti/k3-am62l.dtsi
> new file mode 100644
> index 0000000000000..43da8e52278ce
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62l.dtsi
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: GPL-2.0-only or MIT
> +/*
> + * Device Tree Source for AM62L SoC Family
> + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + *
> + * Tecnical Reference Manual: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "k3-pinctrl.h"
> +
> +/ {
> + model = "Texas Instruments K3 AM62L3 SoC";
> + compatible = "ti,am62l3";
> + interrupt-parent = <&gic500>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> + };
> +
> + a53_timer0: timer-cl0-cpu0 {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
> + };
> +
> + pmu: pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + cbass_main: bus@f0000 {
> + compatible = "simple-bus";
> + ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
> + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
> + <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00040000>, /* GTC */
> + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
> + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */
> + <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */
> + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x0bd28000>, /* Second peripheral window */
> + <0x00 0x30200000 0x00 0x30200000 0x00 0x00400000>, /* DSS */
> + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
> + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
> + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00001000>, /* GPMC0 */
> + <0x00 0x47000000 0x00 0x47000000 0x00 0x02000000>, /* DMSS */
> + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */
> + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
> + <0x00 0x70800000 0x00 0x70800000 0x00 0x00010000>, /* OCSRAM */
> + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
> +
> + /* Wakeup Domain Range */
> + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
> + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
> + <0x00 0x04201000 0x00 0x04201000 0x00 0x00008000>, /* GPIO */
> + <0x00 0x2b100000 0x00 0x2b000000 0x00 0x00200400>, /* TIMER */
> + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
> + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cbass_wakeup: bus@43000000 {
Some odd whitespace indent here and below in this node.
Andrew
> + compatible = "simple-bus";
> + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
> + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
> + <0x00 0x04201000 0x00 0x04201000 0x00 0x00008000>, /* GPIO */
> + <0x00 0x2b100000 0x00 0x2b000000 0x00 0x00200400>, /* TIMER */
> + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
> + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
> + #address-cells = <2>;
> + #size-cells = <2>;
> + bootph-all;
> + };
> + };
> +};
> +
> +/* Now include peripherals for each bus segment */
> +#include "k3-am62l-main.dtsi"
> +#include "k3-am62l-wakeup.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
> new file mode 100644
> index 0000000000000..7dfc869fbce08
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: GPL-2.0-only or MIT
> +/*
> + * Device Tree file for the AM62L3 SoC family (Dual Core A53)
> + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + *
> + * Technical Reference Manual: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-am62l.dtsi"
> +
> +/ {
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0: cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + };
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + cache-size = <0x40000>;
> + cache-line-size = <64>;
> + cache-sets = <256>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> index 22b8d73cfd326..56abfe1790bee 100644
> --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
> +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> @@ -47,6 +47,8 @@
> #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
> #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
>
> +#define AM62LX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
> +
> #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
> #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
>
>
On November 18, 2024 thus sayeth Andrew Davis:
> On 11/17/24 11:34 PM, Bryan Brattlof wrote:
> > From: Vignesh Raghavendra <vigneshr@ti.com>
> >
> > Add the initial infrastructure needed for the AM62L. All of which can be
> > found in the Technical Reference Manual (TRM) located here:
> >
> > https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf
>
> We usually use the non-direct links, that way they can be updated
> to the latest, so here and everywhere below:
>
> https://www.ti.com/lit/pdf/sprujb4
>
> Also might be good to get the TRM folks to now drop the
> "Confidential NDA" watermarks..
>
That's a good point. I'll use the non-direct link
..
> > + cbass_wakeup: bus@43000000 {
>
> Some odd whitespace indent here and below in this node.
>
Nice! I'll fix this up in the next revision
~Bryan
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