Add debug prints to allow to debug the sensor based on dynamic debug.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 drivers/iio/accel/adxl345_core.c | 95 ++++++++++++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c
index 8025dfeb84..e416a50dd0 100644
--- a/drivers/iio/accel/adxl345_core.c
+++ b/drivers/iio/accel/adxl345_core.c
@@ -26,6 +26,9 @@
 
 #include "adxl345.h"
 
+/* debugging registers */
+#define DEBUG_ADXL345 0
+
 /* ADXL345 register map */
 #define ADXL345_REG_DEVID		0x00 /* r    Device ID */
 #define ADXL345_REG_THRESH_TAP	0x1D /* r/w  Tap Threshold */
@@ -181,6 +184,78 @@ static const struct iio_chan_spec adxl34x_channels[] = {
 	ADXL34x_CHANNEL(2, chan_z, Z),
 };
 
+/*
+ * Debugging
+ */
+
+__maybe_unused
+static void adxl345_debug_registers(const char *func, struct adxl34x_state *st)
+{
+#if DEBUG_ADXL345 == 1
+	struct regmap *regmap = st->regmap;
+	unsigned int regval = 0;
+
+	regmap_read(regmap, ADXL345_REG_THRESH_TAP, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_THRESH_TAP\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_DUR, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_DUR\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_LATENT, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_LATENT\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_WINDOW, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_WINDOW\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_ACT_TAP_STATUS, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_ACT_TAP_STATUS\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_POWER_CTL, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_POWER_CTL\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_INT_ENABLE, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_INT_ENABLE\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_INT_MAP, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_INT_MAP\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_INT_SOURCE, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_INT_SOURCE\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_FIFO_CTL, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_FIFO_CTL\n",
+			func, 0xff & regval);
+
+	regmap_read(regmap, ADXL345_REG_FIFO_STATUS, &regval);
+	pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_FIFO_STATUS\n",
+			func, 0xff & regval);
+# endif
+}
+
+__maybe_unused
+static void adxl345_debug_fifo(const char *func, s16 *fifo_buf, int entries_line)
+{
+#if DEBUG_ADXL345 == 1
+	s16 xval, yval, zval;
+
+	xval = fifo_buf[0 + entries_line];
+	yval = fifo_buf[1 + entries_line];
+	zval = fifo_buf[2 + entries_line];
+
+	pr_debug("%s(): FIFO[%d] - x=%d, y=%d, z=%d\n",
+		func, entries_line/3, xval, yval, zval);
+#endif
+}
+
 static int adxl345_set_interrupts(struct adxl34x_state *st)
 {
 	int ret;
@@ -513,6 +588,8 @@ static int adxl345_read_fifo_elements(struct adxl34x_state *st, int fifo_entries
 	size_t count, ndirs = 3;
 	int i, ret;
 
+	pr_debug("%s(): fifo_entries = %d\n", __func__, fifo_entries);
+
 	count = 2 * ndirs; /* 2 byte per direction */
 	for (i = 0; i < fifo_entries; i++) {
 		ret = regmap_noinc_read(st->regmap, ADXL345_REG_XYZ_BASE,
@@ -522,6 +599,7 @@ static int adxl345_read_fifo_elements(struct adxl34x_state *st, int fifo_entries
 			return -EFAULT;
 		}
 	}
+	adxl345_debug_registers(__func__, st);
 
 	return 0;
 }
@@ -639,6 +717,7 @@ static int adxl345_push_fifo_data(struct iio_dev *indio_dev,
 		if (st->fifo_delay && (fifo_entries > 1))
 			udelay(3);
 
+		adxl345_debug_fifo(__func__, st->fifo_buf, i);
 		iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
 	}
 
@@ -666,6 +745,7 @@ static int adxl345_trig_dready(struct iio_trigger *trig, bool state)
 			 __func__, st->int_map);
 	}
 
+	adxl345_debug_registers(__func__, st);
 	return 0;
 }
 
@@ -697,6 +777,7 @@ static irqreturn_t adxl345_trigger_handler(int irq, void *p)
 	int fifo_entries;
 	int ret;
 
+	pr_debug("%s(): IRQ caught!\n", __func__);
 	ret = adxl345_get_status(st, &int_stat);
 	if (ret < 0)
 		goto err;
@@ -731,6 +812,7 @@ static irqreturn_t adxl345_trigger_handler(int irq, void *p)
 
 	goto done;
 err:
+	pr_debug("%s(): error termination\n", __func__);
 	iio_trigger_notify_done(indio_dev->trig);
 	adxl345_set_measure_en(st, false);
 	adxl345_empty_fifo(st);
@@ -738,6 +820,7 @@ static irqreturn_t adxl345_trigger_handler(int irq, void *p)
 	return IRQ_NONE;
 
 done:
+	pr_debug("%s(): regular termination\n", __func__);
 	return IRQ_HANDLED;
 }
 
@@ -788,6 +871,9 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap,
 	st = iio_priv(indio_dev);
 	st->regmap = regmap;
 
+	dev_dbg(dev, "irq '%d'\n", irq);
+	if (!irq) /* fall back to bypass mode w/o IRQ */
+		dev_dbg(dev, "no IRQ, FIFO mode will stay in BYPASS_MODE\n");
 	st->irq = irq;
 	st->info = device_get_match_data(dev);
 	if (!st->info)
@@ -815,7 +901,11 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap,
 	indio_dev->channels = adxl34x_channels;
 	indio_dev->num_channels = ARRAY_SIZE(adxl34x_channels);
 
+	dev_dbg(dev, "setting up indio_dev ok\n");
+
 	if (setup) {
+		dev_dbg(dev, "setup() was provided\n");
+
 		/* Perform optional initial bus specific configuration */
 		ret = setup(dev, st->regmap);
 		if (ret)
@@ -830,6 +920,8 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap,
 					     "Failed to set data range\n");
 
 	} else {
+		dev_dbg(dev, "No setup() provided\n");
+
 		/* Enable full-resolution mode (init all data_format bits) */
 		ret = regmap_write(st->regmap, ADXL345_REG_DATA_FORMAT,
 				   ADXL345_DATA_FORMAT_FULL_RES);
@@ -838,6 +930,7 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap,
 					     "Failed to set data range\n");
 	}
 
+	dev_dbg(dev, "Retrieving DEVID\n");
 	ret = regmap_read(st->regmap, ADXL345_REG_DEVID, &regval);
 	if (ret < 0)
 		return dev_err_probe(dev, ret, "Error reading device ID\n");
@@ -845,7 +938,9 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap,
 	if (regval != ADXL345_DEVID)
 		return dev_err_probe(dev, -ENODEV, "Invalid device ID: %x, expected %x\n",
 				     regval, ADXL345_DEVID);
+	dev_dbg(dev, "Retrieving DEVID ok\n");
 
+	dev_dbg(dev, "Registering power down function\n");
 	ret = devm_add_action_or_reset(dev, adxl345_powerdown, st);
 	if (ret < 0)
 		return dev_err_probe(dev, ret, "Failed to add action or reset\n");
-- 
2.39.2

Hi Lothar,

kernel test robot noticed the following build warnings:

[auto build test WARNING on jic23-iio/togreg]
[also build test WARNING on linus/master v6.12-rc7 next-20241115]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Lothar-Rubusch/iio-accel-adxl345-fix-comment-on-probe/20241115-190245
base:   https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg
patch link:    https://lore.kernel.org/r/20241114231002.98595-23-l.rubusch%40gmail.com
patch subject: [PATCH 22/22] iio: accel: adxl345: add debug printout
config: x86_64-randconfig-121-20241117 (https://download.01.org/0day-ci/archive/20241118/202411180235.gb4VHLRO-lkp@intel.com/config)
compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241118/202411180235.gb4VHLRO-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411180235.gb4VHLRO-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
   drivers/iio/accel/adxl345_core.c:613:6: sparse: sparse: symbol 'adxl345_empty_fifo' was not declared. Should it be static?
>> drivers/iio/accel/adxl345_core.c:720:46: sparse: sparse: incorrect type in argument 2 (different base types) @@     expected signed short [usertype] *fifo_buf @@     got restricted __le16 * @@
   drivers/iio/accel/adxl345_core.c:720:46: sparse:     expected signed short [usertype] *fifo_buf
   drivers/iio/accel/adxl345_core.c:720:46: sparse:     got restricted __le16 *

vim +720 drivers/iio/accel/adxl345_core.c

   606	
   607	/**
   608	 * Empty the fifo. This is needed also in case of overflow or error handling.
   609	 * Read out all remaining elements and reset the fifo_entries counter.
   610	 *
   611	 * @st: The instance to the state object of the sensor.
   612	 */
 > 613	void adxl345_empty_fifo(struct adxl34x_state *st)
   614	{
   615		int regval;
   616		int fifo_entries;
   617	
   618		/* In case the HW is not "clean" just read out remaining elements */
   619		adxl345_get_fifo_entries(st, &fifo_entries);
   620		if (fifo_entries > 0)
   621			adxl345_read_fifo_elements(st, fifo_entries);
   622	
   623		/* Reset the INT_SOURCE register by reading the register */
   624		regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, &regval);
   625	}
   626	
   627	static int adxl345_buffer_postenable(struct iio_dev *indio_dev)
   628	{
   629		struct adxl34x_state *st = iio_priv(indio_dev);
   630		struct adxl34x_platform_data *data = &st->data;
   631		int ret;
   632	
   633		ret = adxl345_set_interrupts(st);
   634		if (ret)
   635			return -EINVAL;
   636	
   637		/* Default to FIFO mode: STREAM, since it covers the general usage
   638		 * and does not bypass the FIFO
   639		 */
   640		data->fifo_mode = ADXL_FIFO_STREAM;
   641		adxl345_set_fifo(st);
   642	
   643		return 0;
   644	}
   645	
   646	static int adxl345_buffer_predisable(struct iio_dev *indio_dev)
   647	{
   648		struct adxl34x_state *st = iio_priv(indio_dev);
   649		struct adxl34x_platform_data *data = &st->data;
   650		int ret;
   651	
   652		/* Turn off interrupts */
   653		st->int_map = 0x00;
   654	
   655		ret = adxl345_set_interrupts(st);
   656		if (ret) {
   657			pr_warn("%s(): Failed to disable INTs\n", __func__);
   658			return -EINVAL;
   659		}
   660	
   661		/* Set FIFO mode: BYPASS, according to the situation */
   662		data->fifo_mode = ADXL_FIFO_BYPASS;
   663		adxl345_set_fifo(st);
   664	
   665		return 0;
   666	}
   667	
   668	static const struct iio_buffer_setup_ops adxl345_buffer_ops = {
   669		.postenable = adxl345_buffer_postenable,
   670		.predisable = adxl345_buffer_predisable,
   671	};
   672	
   673	static int adxl345_get_status(struct adxl34x_state *st, u8 *int_stat)
   674	{
   675		int ret;
   676		unsigned int regval;
   677	
   678		*int_stat = 0;
   679		ret = regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, &regval);
   680		if (ret) {
   681			pr_warn("%s(): Failed to read INT_SOURCE register\n", __func__);
   682			return -EINVAL;
   683		}
   684	
   685		*int_stat = 0xff & regval;
   686		pr_debug("%s(): int_stat 0x%02X (INT_SOURCE)\n", __func__, *int_stat);
   687	
   688		return 0;
   689	}
   690	
   691	static int adxl345_push_fifo_data(struct iio_dev *indio_dev,
   692					  u8 status,
   693					  int fifo_entries)
   694	{
   695		struct adxl34x_state *st = iio_priv(indio_dev);
   696		int ndirs = 3; /* 3 directions */
   697		int i, ret;
   698	
   699		if (fifo_entries <= 0)
   700			return true;
   701	
   702		ret = adxl345_read_fifo_elements(st, fifo_entries);
   703		if (ret)
   704			return false;
   705	
   706		for (i = 0; i < ndirs * fifo_entries; i += ndirs) {
   707			/* To ensure that the FIFO has completely popped, there must be at least 5
   708			 * us between the end of reading the data registers, signified by the
   709			 * transition to register 0x38 from 0x37 or the CS pin going high, and the
   710			 * start of new reads of the FIFO or reading the FIFO_STATUS register. For
   711			 * SPI operation at 1.5 MHz or lower, the register addressing portion of the
   712			 * transmission is sufficient delay to ensure the FIFO has completely
   713			 * popped. It is necessary for SPI operation greater than 1.5 MHz to
   714			 * de-assert the CS pin to ensure a total of 5 us, which is at most 3.4 us
   715			 * at 5 MHz operation.
   716			 */
   717			if (st->fifo_delay && (fifo_entries > 1))
   718				udelay(3);
   719	
 > 720			adxl345_debug_fifo(__func__, st->fifo_buf, i);
   721			iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
   722		}
   723	
   724		return true;
   725	}
   726	

-- 
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https://github.com/intel/lkp-tests/wiki