[v2] Add support to scale DDR and L3 on SA8775P

[PATCH v2 0/2] Add support to scale DDR and L3 on SA8775P

Posted by Jagadeesh Kona 1 year, 2 months ago

Add support to scale DDR and L3 frequencies
based on CPU frequencies on Qualcomm SA8775P
platform. Also add LMH interrupts in cpufreq_hw
node to indicate if there is any thermal throttle.

The changes in this series are dependent on below series changes:
https://lore.kernel.org/all/20241112075826.28296-1-quic_rlaggysh@quicinc.com/

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
Changes in v2:
- Squashed 1st and 2nd patches into a single patch as per review
  comments.
- Alinged the & properly for ICC phandles in CPU DT nodes.
- Updated the commit text for LMH interrupts patch.
- Link to v1: https://lore.kernel.org/r/20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com

---
Jagadeesh Kona (2):
      arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
      arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node

 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 215 ++++++++++++++++++++++++++++++++++
 1 file changed, 215 insertions(+)
---
base-commit: c38b541e924a8c5494db67b0ebf04cbcd84ca767
change-id: 20241112-sa8775p-cpufreq-l3-ddr-scaling-e10b3d71a80b

Best regards,
-- 
Jagadeesh Kona <quic_jkona@quicinc.com>

Re: [PATCH v2 0/2] Add support to scale DDR and L3 on SA8775P

Posted by Bjorn Andersson 10 months, 3 weeks ago

On Tue, 12 Nov 2024 18:14:10 +0530, Jagadeesh Kona wrote:
> Add support to scale DDR and L3 frequencies
> based on CPU frequencies on Qualcomm SA8775P
> platform. Also add LMH interrupts in cpufreq_hw
> node to indicate if there is any thermal throttle.
> 
> The changes in this series are dependent on below series changes:
> https://lore.kernel.org/all/20241112075826.28296-1-quic_rlaggysh@quicinc.com/
> 
> [...]

Applied, thanks!

[1/2] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
      (no commit info)
[2/2] arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node
      commit: cc13a858a79d8c5798a99e8cde677ea36272a5a0

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH v2 0/2] Add support to scale DDR and L3 on SA8775P

Posted by Jagadeesh Kona 10 months, 3 weeks ago


On 3/17/2025 8:25 AM, Bjorn Andersson wrote:
> 
> On Tue, 12 Nov 2024 18:14:10 +0530, Jagadeesh Kona wrote:
>> Add support to scale DDR and L3 frequencies
>> based on CPU frequencies on Qualcomm SA8775P
>> platform. Also add LMH interrupts in cpufreq_hw
>> node to indicate if there is any thermal throttle.
>>
>> The changes in this series are dependent on below series changes:
>> https://lore.kernel.org/all/20241112075826.28296-1-quic_rlaggysh@quicinc.com/
>>
>> [...]
> 
> Applied, thanks!
> 
> [1/2] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
>       (no commit info)

Hi Bjorn, I am not sure if above DDR/L3 scaling commit is picked here, but as per
our earlier discussion[1], I have included the above patch in the dependent
interconnect series[2].

Above DDR/L3 scaling patch cannot be picked alone without interconnect changes, as it
will lead to compilation errors.

[1]: https://lore.kernel.org/all/d649eac7-c9bb-48f9-a5d7-758688b85107@quicinc.com/
[2]: https://lore.kernel.org/all/20250227155213.404-1-quic_rlaggysh@quicinc.com/

Thanks,
Jagadeesh

> [2/2] arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node
>       commit: cc13a858a79d8c5798a99e8cde677ea36272a5a0
> 
> Best regards,

Re: [PATCH v2 0/2] Add support to scale DDR and L3 on SA8775P

Posted by Bjorn Andersson 1 year, 1 month ago

On Tue, Nov 12, 2024 at 06:14:10PM +0530, Jagadeesh Kona wrote:
> Add support to scale DDR and L3 frequencies
> based on CPU frequencies on Qualcomm SA8775P
> platform. Also add LMH interrupts in cpufreq_hw
> node to indicate if there is any thermal throttle.
> 
> The changes in this series are dependent on below series changes:
> https://lore.kernel.org/all/20241112075826.28296-1-quic_rlaggysh@quicinc.com/

This dependency didn't materialize, so I can only guess that this patch
will have to be changed accordingly. As such, I'm dropping your series
from my queue as well.

It would be much appreciated if you send such tightly dependent 
patches together in the same series in the future.

Regards,
Bjorn

> 
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
> Changes in v2:
> - Squashed 1st and 2nd patches into a single patch as per review
>   comments.
> - Alinged the & properly for ICC phandles in CPU DT nodes.
> - Updated the commit text for LMH interrupts patch.
> - Link to v1: https://lore.kernel.org/r/20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com
> 
> ---
> Jagadeesh Kona (2):
>       arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
>       arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node
> 
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 215 ++++++++++++++++++++++++++++++++++
>  1 file changed, 215 insertions(+)
> ---
> base-commit: c38b541e924a8c5494db67b0ebf04cbcd84ca767
> change-id: 20241112-sa8775p-cpufreq-l3-ddr-scaling-e10b3d71a80b
> 
> Best regards,
> -- 
> Jagadeesh Kona <quic_jkona@quicinc.com>
>

Re: [PATCH v2 0/2] Add support to scale DDR and L3 on SA8775P

Posted by Jagadeesh Kona 1 year ago


On 12/27/2024 10:05 AM, Bjorn Andersson wrote:
> On Tue, Nov 12, 2024 at 06:14:10PM +0530, Jagadeesh Kona wrote:
>> Add support to scale DDR and L3 frequencies
>> based on CPU frequencies on Qualcomm SA8775P
>> platform. Also add LMH interrupts in cpufreq_hw
>> node to indicate if there is any thermal throttle.
>>
>> The changes in this series are dependent on below series changes:
>> https://lore.kernel.org/all/20241112075826.28296-1-quic_rlaggysh@quicinc.com/
> 
> This dependency didn't materialize, so I can only guess that this patch
> will have to be changed accordingly. As such, I'm dropping your series
> from my queue as well.
> 
> It would be much appreciated if you send such tightly dependent 
> patches together in the same series in the future.
> 

Thanks Bjorn for your review!

Sure, will send the DDR & L3 scaling change along with the dependent patch series,
and will post the LMH interrupt patch separately as it is independent. 

Thanks,
Jagadeesh

> Regards,
> Bjorn
> 
>>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> ---
>> Changes in v2:
>> - Squashed 1st and 2nd patches into a single patch as per review
>>   comments.
>> - Alinged the & properly for ICC phandles in CPU DT nodes.
>> - Updated the commit text for LMH interrupts patch.
>> - Link to v1: https://lore.kernel.org/r/20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com
>>
>> ---
>> Jagadeesh Kona (2):
>>       arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
>>       arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node
>>
>>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 215 ++++++++++++++++++++++++++++++++++
>>  1 file changed, 215 insertions(+)
>> ---
>> base-commit: c38b541e924a8c5494db67b0ebf04cbcd84ca767
>> change-id: 20241112-sa8775p-cpufreq-l3-ddr-scaling-e10b3d71a80b
>>
>> Best regards,
>> -- 
>> Jagadeesh Kona <quic_jkona@quicinc.com>
>>