[v2] Add support to scale DDR and L3 on SA8775P

[PATCH v2 0/2] Add support to scale DDR and L3 on SA8775P

Jagadeesh Kona posted 2 patches 1 week, 3 days ago

Diff against v1
Download series mbox

arch/arm64/boot/dts/qcom/sa8775p.dtsi | 215 ++++++++++++++++++++++++++++++++++
1 file changed, 215 insertions(+)

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[PATCH v2 0/2] Add support to scale DDR and L3 on SA8775P

Posted by Jagadeesh Kona 1 week, 3 days ago

Add support to scale DDR and L3 frequencies
based on CPU frequencies on Qualcomm SA8775P
platform. Also add LMH interrupts in cpufreq_hw
node to indicate if there is any thermal throttle.

The changes in this series are dependent on below series changes:
https://lore.kernel.org/all/20241112075826.28296-1-quic_rlaggysh@quicinc.com/

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
Changes in v2:
- Squashed 1st and 2nd patches into a single patch as per review
  comments.
- Alinged the & properly for ICC phandles in CPU DT nodes.
- Updated the commit text for LMH interrupts patch.
- Link to v1: https://lore.kernel.org/r/20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com

---
Jagadeesh Kona (2):
      arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
      arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node

 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 215 ++++++++++++++++++++++++++++++++++
 1 file changed, 215 insertions(+)
---
base-commit: c38b541e924a8c5494db67b0ebf04cbcd84ca767
change-id: 20241112-sa8775p-cpufreq-l3-ddr-scaling-e10b3d71a80b

Best regards,
-- 
Jagadeesh Kona <quic_jkona@quicinc.com>