Add the 'sam9x75-mipi-dsi' compatible binding, which describes the
Microchip's specific wrapper for the Synopsys DesignWare MIPI DSI HOST
Controller for the sam9x75 series System-on-Chip (SoC) devices.
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
changes in v5:
- Add reviewed-by tag
changes in v4:
- Removed 'microchip,sfr' phandle property since
regmap to SFR node can be obtained using its compatible
string
changes in v3:
- Describe the clocks used
changes in v2:
- List the clocks with description
- remove describing 'remove-endpoint' properties
- remove unused label, node and fix example DT indentation
- cosmetic fixes
---
.../bridge/microchip,sam9x75-mipi-dsi.yaml | 109 ++++++++++++++++++
1 file changed, 109 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml
new file mode 100644
index 000000000000..d2ae6250e1f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/microchip,sam9x75-mipi-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip SAM9X75 MIPI DSI Controller
+
+maintainers:
+ - Manikandan Muralidharan <manikandan.m@microchip.com>
+
+description:
+ Microchip specific extensions or wrapper to the Synopsys Designware MIPI DSI.
+ The MIPI Display Serial Interface (DSI) Host Controller implements all
+ protocol functions defined in the MIPI DSI Specification.The DSI Host
+ provides an interface between the LCD Controller (LCDC) and the MIPI D-PHY,
+ allowing communication with a DSI-compliant display.
+
+allOf:
+ - $ref: /schemas/display/dsi-controller.yaml#
+
+properties:
+ compatible:
+ const: microchip,sam9x75-mipi-dsi
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description:
+ Peripheral Bus Clock between LCDC and MIPI DPHY
+ - description:
+ MIPI DPHY Interface reference clock for PLL block
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: refclk
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ DSI Input port node, connected to the LCDC RGB output port.
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ DSI Output port node, connected to a panel or a bridge input port.
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi@f8054000 {
+ compatible = "microchip,sam9x75-mipi-dsi";
+ reg = <0xf8054000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 55>;
+ clock-names = "pclk", "refclk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&hlcdc_panel_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+ };
+...
--
2.25.1