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[PATCH net-next v3 0/2] net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX

Roger Quadros posted 2 patches 2 weeks ago
There is a newer version of this series
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 54 ++++++++++++++++++++++++++++++++
drivers/net/ethernet/ti/cpsw_ale.c       | 36 ++++++++++++---------
2 files changed, 76 insertions(+), 14 deletions(-)
[PATCH net-next v3 0/2] net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX
Posted by Roger Quadros 2 weeks ago 
Configure DSCP to Priority mapping registers so that IP precedence
field (top 3 bits of DSCP) map it to one of the 8 priority queues
for RX traffic.
    
Also update Priority to Thread maping to be compliant with
IEEE802.1Q-2014. Priority Code Point (PCP) 2 is higher priority than
PCP 0 (Best Effort). PCP 1 (Background) is lower priority than
PCP 0 (Best Effort).

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
Changes in v3:
- Added Reviewed-by tag to patch 1
- Added macros for DSCP PRI field size and DSCP PRI per register
- Drop unnecessary readl() in am65_cpsw_port_set_dscp_map()
- Link to v2: https://lore.kernel.org/r/20241107-am65-cpsw-multi-rx-dscp-v2-0-9e9cd1920035@kernel.org

Changes in v2:
- Updated references to more recent standard IEEE802.1Q-2014.
- Dropped reference to web link which might change in the future.
- Typo fix in commit log.
- Link to v1: https://lore.kernel.org/r/20241105-am65-cpsw-multi-rx-dscp-v1-0-38db85333c88@kernel.org

---
Roger Quadros (2):
      net: ethernet: ti: am65-cpsw: update pri_thread_map as per IEEE802.1Q-2014
      net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX

 drivers/net/ethernet/ti/am65-cpsw-nuss.c | 54 ++++++++++++++++++++++++++++++++
 drivers/net/ethernet/ti/cpsw_ale.c       | 36 ++++++++++++---------
 2 files changed, 76 insertions(+), 14 deletions(-)
---
base-commit: 42f7652d3eb527d03665b09edac47f85fb600924
change-id: 20241101-am65-cpsw-multi-rx-dscp-000b2c4af6d0

Best regards,
-- 
Roger Quadros <rogerq@kernel.org>
Re: [PATCH net-next v3 0/2] net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX
Posted by Simon Horman 1 week, 4 days ago 
+ Ido and Guilliame

On Sat, Nov 09, 2024 at 01:00:06PM +0200, Roger Quadros wrote:
> Configure DSCP to Priority mapping registers so that IP precedence
> field (top 3 bits of DSCP) map it to one of the 8 priority queues
> for RX traffic.
>     
> Also update Priority to Thread maping to be compliant with
> IEEE802.1Q-2014. Priority Code Point (PCP) 2 is higher priority than
> PCP 0 (Best Effort). PCP 1 (Background) is lower priority than
> PCP 0 (Best Effort).
> 
> Signed-off-by: Roger Quadros <rogerq@kernel.org>

Hi Ido and Guilliame,

I am wondering if you could find time to review this series.

> ---
> Changes in v3:
> - Added Reviewed-by tag to patch 1
> - Added macros for DSCP PRI field size and DSCP PRI per register
> - Drop unnecessary readl() in am65_cpsw_port_set_dscp_map()
> - Link to v2: https://lore.kernel.org/r/20241107-am65-cpsw-multi-rx-dscp-v2-0-9e9cd1920035@kernel.org
> 
> Changes in v2:
> - Updated references to more recent standard IEEE802.1Q-2014.
> - Dropped reference to web link which might change in the future.
> - Typo fix in commit log.
> - Link to v1: https://lore.kernel.org/r/20241105-am65-cpsw-multi-rx-dscp-v1-0-38db85333c88@kernel.org
> 
> ---
> Roger Quadros (2):
>       net: ethernet: ti: am65-cpsw: update pri_thread_map as per IEEE802.1Q-2014
>       net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX
> 
>  drivers/net/ethernet/ti/am65-cpsw-nuss.c | 54 ++++++++++++++++++++++++++++++++
>  drivers/net/ethernet/ti/cpsw_ale.c       | 36 ++++++++++++---------
>  2 files changed, 76 insertions(+), 14 deletions(-)
> ---
> base-commit: 42f7652d3eb527d03665b09edac47f85fb600924
> change-id: 20241101-am65-cpsw-multi-rx-dscp-000b2c4af6d0
> 
> Best regards,
> -- 
> Roger Quadros <rogerq@kernel.org>
>
Re: [PATCH net-next v3 0/2] net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX
Posted by Guillaume Nault 1 week, 2 days ago 
On Tue, Nov 12, 2024 at 02:08:33PM +0000, Simon Horman wrote:
> + Ido and Guilliame
> 
> On Sat, Nov 09, 2024 at 01:00:06PM +0200, Roger Quadros wrote:
> > Configure DSCP to Priority mapping registers so that IP precedence
> > field (top 3 bits of DSCP) map it to one of the 8 priority queues
> > for RX traffic.
> >     
> > Also update Priority to Thread maping to be compliant with
> > IEEE802.1Q-2014. Priority Code Point (PCP) 2 is higher priority than
> > PCP 0 (Best Effort). PCP 1 (Background) is lower priority than
> > PCP 0 (Best Effort).
> > 
> > Signed-off-by: Roger Quadros <rogerq@kernel.org>
> 
> Hi Ido and Guilliame,
> 
> I am wondering if you could find time to review this series.

I don't have the IEEE802.1Q-2014 spec at hand, so I focused on
patch 2/2.

> > ---
> > Changes in v3:
> > - Added Reviewed-by tag to patch 1
> > - Added macros for DSCP PRI field size and DSCP PRI per register
> > - Drop unnecessary readl() in am65_cpsw_port_set_dscp_map()
> > - Link to v2: https://lore.kernel.org/r/20241107-am65-cpsw-multi-rx-dscp-v2-0-9e9cd1920035@kernel.org
> > 
> > Changes in v2:
> > - Updated references to more recent standard IEEE802.1Q-2014.
> > - Dropped reference to web link which might change in the future.
> > - Typo fix in commit log.
> > - Link to v1: https://lore.kernel.org/r/20241105-am65-cpsw-multi-rx-dscp-v1-0-38db85333c88@kernel.org
> > 
> > ---
> > Roger Quadros (2):
> >       net: ethernet: ti: am65-cpsw: update pri_thread_map as per IEEE802.1Q-2014
> >       net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX
> > 
> >  drivers/net/ethernet/ti/am65-cpsw-nuss.c | 54 ++++++++++++++++++++++++++++++++
> >  drivers/net/ethernet/ti/cpsw_ale.c       | 36 ++++++++++++---------
> >  2 files changed, 76 insertions(+), 14 deletions(-)
> > ---
> > base-commit: 42f7652d3eb527d03665b09edac47f85fb600924
> > change-id: 20241101-am65-cpsw-multi-rx-dscp-000b2c4af6d0
> > 
> > Best regards,
> > -- 
> > Roger Quadros <rogerq@kernel.org>
> > 
>
Re: [PATCH net-next v3 0/2] net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX
Posted by Roger Quadros 1 week, 2 days ago 
Hi Guillaume,

On 14/11/2024 02:19, Guillaume Nault wrote:
> On Tue, Nov 12, 2024 at 02:08:33PM +0000, Simon Horman wrote:
>> + Ido and Guilliame
>>
>> On Sat, Nov 09, 2024 at 01:00:06PM +0200, Roger Quadros wrote:
>>> Configure DSCP to Priority mapping registers so that IP precedence
>>> field (top 3 bits of DSCP) map it to one of the 8 priority queues
>>> for RX traffic.
>>>     
>>> Also update Priority to Thread maping to be compliant with
>>> IEEE802.1Q-2014. Priority Code Point (PCP) 2 is higher priority than
>>> PCP 0 (Best Effort). PCP 1 (Background) is lower priority than
>>> PCP 0 (Best Effort).
>>>
>>> Signed-off-by: Roger Quadros <rogerq@kernel.org>
>>
>> Hi Ido and Guilliame,
>>
>> I am wondering if you could find time to review this series.
> 
> I don't have the IEEE802.1Q-2014 spec at hand, so I focused on
> patch 2/2.

You can look at an older spec along with this page
https://en.wikipedia.org/wiki/IEEE_P802.1p#Priority_levels

> 
>>> ---
>>> Changes in v3:
>>> - Added Reviewed-by tag to patch 1
>>> - Added macros for DSCP PRI field size and DSCP PRI per register
>>> - Drop unnecessary readl() in am65_cpsw_port_set_dscp_map()
>>> - Link to v2: https://lore.kernel.org/r/20241107-am65-cpsw-multi-rx-dscp-v2-0-9e9cd1920035@kernel.org
>>>
>>> Changes in v2:
>>> - Updated references to more recent standard IEEE802.1Q-2014.
>>> - Dropped reference to web link which might change in the future.
>>> - Typo fix in commit log.
>>> - Link to v1: https://lore.kernel.org/r/20241105-am65-cpsw-multi-rx-dscp-v1-0-38db85333c88@kernel.org
>>>
>>> ---
>>> Roger Quadros (2):
>>>       net: ethernet: ti: am65-cpsw: update pri_thread_map as per IEEE802.1Q-2014
>>>       net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX
>>>
>>>  drivers/net/ethernet/ti/am65-cpsw-nuss.c | 54 ++++++++++++++++++++++++++++++++
>>>  drivers/net/ethernet/ti/cpsw_ale.c       | 36 ++++++++++++---------
>>>  2 files changed, 76 insertions(+), 14 deletions(-)
>>> ---
>>> base-commit: 42f7652d3eb527d03665b09edac47f85fb600924
>>> change-id: 20241101-am65-cpsw-multi-rx-dscp-000b2c4af6d0
>>>
>>> Best regards,
>>> -- 
>>> Roger Quadros <rogerq@kernel.org>
>>>
>>
> 

-- 
cheers,
-roger

Patchew 2.1-devel-b67e4c2

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