SoC with CCI architecture should set transition_delay to 10 ms because
cpufreq need to call devfreq notifier in async mode. if delay less than
10 ms, it may get wrong OPP-level in devfreq passive governor.

Signed-off-by: Mark Tseng <chun-jen.tseng@mediatek.com>
---
 drivers/cpufreq/mediatek-cpufreq.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 663f61565cf7..f63183154e9a 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -597,6 +597,9 @@ static int mtk_cpufreq_init(struct cpufreq_policy *policy)
 	policy->driver_data = info;
 	policy->clk = info->cpu_clk;
 
+	if (info->soc_data->ccifreq_supported)
+		policy->transition_delay_us = 10000;
+
 	return 0;
 }
 
-- 
2.45.2

Il 08/11/24 07:39, Mark Tseng ha scritto:
> SoC with CCI architecture should set transition_delay to 10 ms because
> cpufreq need to call devfreq notifier in async mode. if delay less than
> 10 ms, it may get wrong OPP-level in devfreq passive governor.
> 

This means that MediaTek SoCs can change their CPU frequency once every
10 milliseconds?!?!?!

I don't think that's really the case.

Besides, are you aware that this will have a *huge* impact on either power
consumption or performance?
We're going from a bunch of microseconds to *multiple* milliseconds here.

Regards,
Angelo