Convert the bindings to yaml format.
Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
---
.../devicetree/bindings/mtd/davinci-nand.txt | 94 ---------------
.../devicetree/bindings/mtd/ti,davinci-nand.yaml | 134 +++++++++++++++++++++
2 files changed, 134 insertions(+), 94 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
deleted file mode 100644
index eb8e2ff4dbd2901b3c396f2e66c1f590a32dcf67..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-Device tree bindings for Texas instruments Davinci/Keystone NAND controller
-
-This file provides information, what the device node for the davinci/keystone
-NAND interface contains.
-
-Documentation:
-Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
-Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
-
-Required properties:
-
-- compatible: "ti,davinci-nand"
- "ti,keystone-nand"
-
-- reg: Contains 2 offset/length values:
- - offset and length for the access window.
- - offset and length for accessing the AEMIF
- control registers.
-
-- ti,davinci-chipselect: number of chipselect. Indicates on the
- davinci_nand driver which chipselect is used
- for accessing the nand.
- Can be in the range [0-3].
-
-Recommended properties :
-
-- ti,davinci-mask-ale: mask for ALE. Needed for executing address
- phase. These offset will be added to the base
- address for the chip select space the NAND Flash
- device is connected to.
- If not set equal to 0x08.
-
-- ti,davinci-mask-cle: mask for CLE. Needed for executing command
- phase. These offset will be added to the base
- address for the chip select space the NAND Flash
- device is connected to.
- If not set equal to 0x10.
-
-- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
- addresses for given chipselect.
-
-- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
- valid values for davinci driver:
- - "none"
- - "soft"
- - "hw"
-
-- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
-
-- nand-bus-width: buswidth 8 or 16. If not present 8.
-
-- nand-on-flash-bbt: use flash based bad block table support. OOB
- identifier is saved in OOB area. If not present
- false.
-
-Deprecated properties:
-
-- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
- valid values for davinci driver:
- - "none"
- - "soft"
- - "hw"
-
-- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
-
-- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
- identifier is saved in OOB area. If not present
- false.
-
-Nand device bindings may contain additional sub-nodes describing partitions of
-the address space. See mtd.yaml for more detail. The NAND Flash timing
-values must be programmed in the chip select’s node of AEMIF
-memory-controller (see Documentation/devicetree/bindings/memory-controllers/
-davinci-aemif.txt).
-
-Example(da850 EVM ):
-
-nand_cs3@62000000 {
- compatible = "ti,davinci-nand";
- reg = <0x62000000 0x807ff
- 0x68000000 0x8000>;
- ti,davinci-chipselect = <1>;
- ti,davinci-mask-ale = <0>;
- ti,davinci-mask-cle = <0>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x7e80000>;
- };
-};
diff --git a/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..fffdaa9bf85ac2ffb1b177bdc693c995d2a8ea20
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI DaVinci NAND controller
+
+maintainers:
+ - Marcus Folkesson <marcus.folkesson@gmail.com>
+
+allOf:
+ - $ref: nand-controller.yaml
+
+properties:
+ compatible:
+ enum:
+ - ti,davinci-nand
+ - ti,keystone-nand
+
+ reg:
+ items:
+ - description:
+ Access window.
+ - description:
+ AEMIF control registers
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ partitions:
+ $ref: /schemas/mtd/partitions/partitions.yaml
+
+ ti,davinci-chipselect:
+ description:
+ Number of chipselect. Indicate on the davinci_nand driver which
+ chipselect is used for accessing the nand.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+
+ ti,davinci-mask-ale:
+ description:
+ Mask for ALE. Needed for executing address phase. These offset will be
+ added to the base address for the chip select space the NAND Flash
+ device is connected to.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x08
+
+ ti,davinci-mask-cle:
+ description:
+ Mask for CLE. Needed for executing command phase. These offset will be
+ added to the base address for the chip select space the NAND Flash device
+ is connected to.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x10
+
+ ti,davinci-mask-chipsel:
+ description:
+ Mask for chipselect address. Needed to mask addresses for given
+ chipselect.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ ti,davinci-ecc-bits:
+ description: Used ECC bits.
+ enum: [1, 4]
+
+ ti,davinci-ecc-mode:
+ description: Operation mode of the NAND ECC mode.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [none, soft, hw, on-die]
+ deprecated: true
+
+ ti,davinci-nand-buswidth:
+ description: Bus width to the NAND chip
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [8, 16]
+ default: 8
+ deprecated: true
+
+ ti,davinci-nand-use-bbt:
+ type: boolean
+ description:
+ Use flash based bad block table support. OOB identifier is saved in OOB
+ area.
+ deprecated: true
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ti,davinci-chipselect
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ nand-controller@2000000,0 {
+ compatible = "ti,davinci-nand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x02000000 0x02000000
+ 1 0x00000000 0x00008000>;
+
+ ti,davinci-chipselect = <1>;
+ ti,davinci-mask-ale = <0>;
+ ti,davinci-mask-cle = <0>;
+ ti,davinci-mask-chipsel = <0>;
+
+ ti,davinci-nand-buswidth = <16>;
+ ti,davinci-ecc-mode = "hw";
+ ti,davinci-ecc-bits = <4>;
+ ti,davinci-nand-use-bbt;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot env";
+ reg = <0 0x020000>;
+ };
+ };
+ };
+ };
--
2.47.0
On Thu, Nov 07, 2024 at 10:19:54AM +0100, Marcus Folkesson wrote:
> Convert the bindings to yaml format.
>
> Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
> ---
> .../devicetree/bindings/mtd/davinci-nand.txt | 94 ---------------
> .../devicetree/bindings/mtd/ti,davinci-nand.yaml | 134 +++++++++++++++++++++
> 2 files changed, 134 insertions(+), 94 deletions(-)
...
> +allOf:
> + - $ref: nand-controller.yaml
> +
> +properties:
> + compatible:
> + enum:
> + - ti,davinci-nand
> + - ti,keystone-nand
> +
> + reg:
> + items:
> + - description:
> + Access window.
Merge two lines. See other files how they do it.
> + - description:
> + AEMIF control registers
Merge two lines
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
These two properties are not needed, drop. I don't understand why did
they appear here. Changelog also does no explain it.
> +
> + partitions:
> + $ref: /schemas/mtd/partitions/partitions.yaml
> +
> + ti,davinci-chipselect:
> + description:
> + Number of chipselect. Indicate on the davinci_nand driver which
> + chipselect is used for accessing the nand.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3]
> +
> + ti,davinci-mask-ale:
> + description:
> + Mask for ALE. Needed for executing address phase. These offset will be
> + added to the base address for the chip select space the NAND Flash
> + device is connected to.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0x08
> +
> + ti,davinci-mask-cle:
> + description:
> + Mask for CLE. Needed for executing command phase. These offset will be
> + added to the base address for the chip select space the NAND Flash device
> + is connected to.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0x10
> +
> + ti,davinci-mask-chipsel:
> + description:
> + Mask for chipselect address. Needed to mask addresses for given
> + chipselect.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> +
> + ti,davinci-ecc-bits:
> + description: Used ECC bits.
> + enum: [1, 4]
> +
> + ti,davinci-ecc-mode:
> + description: Operation mode of the NAND ECC mode.
> + $ref: /schemas/types.yaml#/definitions/string
> + enum: [none, soft, hw, on-die]
> + deprecated: true
> +
> + ti,davinci-nand-buswidth:
> + description: Bus width to the NAND chip
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [8, 16]
> + default: 8
> + deprecated: true
> +
> + ti,davinci-nand-use-bbt:
> + type: boolean
> + description:
> + Use flash based bad block table support. OOB identifier is saved in OOB
> + area.
> + deprecated: true
> +
> +required:
> + - compatible
> + - reg
> + - "#address-cells"
> + - "#size-cells"
Drop these two.
> + - ti,davinci-chipselect
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + bus {
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + nand-controller@2000000,0 {
> + compatible = "ti,davinci-nand";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x02000000 0x02000000
> + 1 0x00000000 0x00008000>;
Two items must be encoded as two items, so two <> <>
Also messed alignment. See DTS coding style.
> +
> + ti,davinci-chipselect = <1>;
> + ti,davinci-mask-ale = <0>;
> + ti,davinci-mask-cle = <0>;
> + ti,davinci-mask-chipsel = <0>;
> +
> + ti,davinci-nand-buswidth = <16>;
> + ti,davinci-ecc-mode = "hw";
> + ti,davinci-ecc-bits = <4>;
> + ti,davinci-nand-use-bbt;
> +
> + partitions {
Where are the partitions documented? In which binding? Don't you miss
mtd.yaml? I think this binding misses some references, but I am not sure
which ones.
Best regards,
Krzysztof
On Thu, Nov 07, 2024 at 11:17:14AM +0100, Krzysztof Kozlowski wrote:
> On Thu, Nov 07, 2024 at 10:19:54AM +0100, Marcus Folkesson wrote:
> > Convert the bindings to yaml format.
> >
> > Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
> > ---
> > .../devicetree/bindings/mtd/davinci-nand.txt | 94 ---------------
> > .../devicetree/bindings/mtd/ti,davinci-nand.yaml | 134 +++++++++++++++++++++
> > 2 files changed, 134 insertions(+), 94 deletions(-)
>
> ...
>
> > +allOf:
> > + - $ref: nand-controller.yaml
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - ti,davinci-nand
> > + - ti,keystone-nand
> > +
> > + reg:
> > + items:
> > + - description:
> > + Access window.
>
> Merge two lines. See other files how they do it.
Ok
>
> > + - description:
> > + AEMIF control registers
>
> Merge two lines
Ok
>
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 0
>
> These two properties are not needed, drop. I don't understand why did
> they appear here. Changelog also does no explain it.
Ok, I drop those.
[...]
> > +examples:
> > + - |
> > + bus {
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > +
> > + nand-controller@2000000,0 {
> > + compatible = "ti,davinci-nand";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0 0x02000000 0x02000000
> > + 1 0x00000000 0x00008000>;
>
> Two items must be encoded as two items, so two <> <>
> Also messed alignment. See DTS coding style.
Ok
>
> > +
> > + ti,davinci-chipselect = <1>;
> > + ti,davinci-mask-ale = <0>;
> > + ti,davinci-mask-cle = <0>;
> > + ti,davinci-mask-chipsel = <0>;
> > +
> > + ti,davinci-nand-buswidth = <16>;
> > + ti,davinci-ecc-mode = "hw";
> > + ti,davinci-ecc-bits = <4>;
> > + ti,davinci-nand-use-bbt;
> > +
> > + partitions {
>
> Where are the partitions documented? In which binding? Don't you miss
> mtd.yaml? I think this binding misses some references, but I am not sure
> which ones.
I thought this covered it?
+ partitions:
+ $ref: /schemas/mtd/partitions/partitions.yaml
>
> Best regards,
> Krzysztof
>
Thanks,
Marcus Folkesson
On 07/11/2024 13:23, Marcus Folkesson wrote:
>>
>>> +
>>> + ti,davinci-chipselect = <1>;
>>> + ti,davinci-mask-ale = <0>;
>>> + ti,davinci-mask-cle = <0>;
>>> + ti,davinci-mask-chipsel = <0>;
>>> +
>>> + ti,davinci-nand-buswidth = <16>;
>>> + ti,davinci-ecc-mode = "hw";
>>> + ti,davinci-ecc-bits = <4>;
>>> + ti,davinci-nand-use-bbt;
>>> +
>>> + partitions {
>>
>> Where are the partitions documented? In which binding? Don't you miss
>> mtd.yaml? I think this binding misses some references, but I am not sure
>> which ones.
>
> I thought this covered it?
>
> + partitions:
> + $ref: /schemas/mtd/partitions/partitions.yaml
O, yes, I somehow totally missed it. It's fine, thanks for explaining.
Best regards,
Krzysztof
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