Add support for restricting the port's link width by specifying
the num-lanes devicetree property in the PCIe node.
The setting is done in the GEN_SETTINGS register (in the driver
named as PCIE_SETTING_REG), where each set bit in [11:8] activates
a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2).
Reviewed-by: Fei Shao <fshao@chromium.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/pci/controller/pcie-mediatek-gen3.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index c27beef75079..fa7f36a0284d 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -32,6 +32,7 @@
#define PCIE_BASE_CFG_SPEED GENMASK(15, 8)
#define PCIE_SETTING_REG 0x80
+#define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8)
#define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12)
#define PCIE_PCI_IDS_1 0x9c
#define PCI_CLASS(class) (class << 8)
@@ -168,6 +169,7 @@ struct mtk_msi_set {
* @clks: PCIe clocks
* @num_clks: PCIe clocks count for this port
* @max_link_speed: Maximum link speed (PCIe Gen) for this port
+ * @num_lanes: Number of PCIe lanes for this port
* @irq: PCIe controller interrupt number
* @saved_irq_state: IRQ enable state saved at suspend time
* @irq_lock: lock protecting IRQ register access
@@ -189,6 +191,7 @@ struct mtk_gen3_pcie {
struct clk_bulk_data *clks;
int num_clks;
u8 max_link_speed;
+ u8 num_lanes;
int irq;
u32 saved_irq_state;
@@ -401,6 +404,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT,
GENMASK(pcie->max_link_speed - 2, 0));
}
+ if (pcie->num_lanes) {
+ val &= ~PCIE_SETTING_LINK_WIDTH;
+
+ /* Zero means one lane, each bit activates x2/x4/x8/x16 */
+ if (pcie->num_lanes > 1)
+ val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH,
+ GENMASK(fls(pcie->num_lanes >> 2), 0));
+ };
writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
/* Set Link Control 2 (LNKCTL2) speed restriction, if any */
@@ -838,6 +849,7 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
struct resource *regs;
+ u32 num_lanes;
regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
if (!regs)
@@ -883,6 +895,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
return pcie->num_clks;
}
+ ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
+ if (ret == 0) {
+ if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
+ dev_warn(dev, "Invalid num-lanes, using controller defaults\n");
+ else
+ pcie->num_lanes = num_lanes;
+ }
+
return 0;
}
--
2.46.1On Mon, Nov 04, 2024 at 12:49:35PM +0100, AngeloGioacchino Del Regno wrote:
> Add support for restricting the port's link width by specifying
> the num-lanes devicetree property in the PCIe node.
>
> The setting is done in the GEN_SETTINGS register (in the driver
> named as PCIE_SETTING_REG), where each set bit in [11:8] activates
> a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2).
I guess GEN_SETTINGS doesn't correspond to a register defined by the
PCIe spec, right? The only thing in the spec that looks similar is
the Target Link Width in the Device Control 3 register, but the bit
position doesn't look like this PCIE_SETTING_LINK_WIDTH mask:
> #define PCIE_SETTING_REG 0x80
> +#define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8)
> #define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12)
> #define PCIE_PCI_IDS_1 0x9c
> #define PCI_CLASS(class) (class << 8)
> @@ -168,6 +169,7 @@ struct mtk_msi_set {
> * @clks: PCIe clocks
> * @num_clks: PCIe clocks count for this port
> * @max_link_speed: Maximum link speed (PCIe Gen) for this port
> + * @num_lanes: Number of PCIe lanes for this port
> * @irq: PCIe controller interrupt number
> * @saved_irq_state: IRQ enable state saved at suspend time
> * @irq_lock: lock protecting IRQ register access
> @@ -189,6 +191,7 @@ struct mtk_gen3_pcie {
> struct clk_bulk_data *clks;
> int num_clks;
> u8 max_link_speed;
> + u8 num_lanes;
>
> int irq;
> u32 saved_irq_state;
> @@ -401,6 +404,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
> val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT,
> GENMASK(pcie->max_link_speed - 2, 0));
> }
> + if (pcie->num_lanes) {
> + val &= ~PCIE_SETTING_LINK_WIDTH;
> +
> + /* Zero means one lane, each bit activates x2/x4/x8/x16 */
> + if (pcie->num_lanes > 1)
> + val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH,
> + GENMASK(fls(pcie->num_lanes >> 2), 0));
> + };
> writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
>
> /* Set Link Control 2 (LNKCTL2) speed restriction, if any */
> @@ -838,6 +849,7 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
> struct device *dev = pcie->dev;
> struct platform_device *pdev = to_platform_device(dev);
> struct resource *regs;
> + u32 num_lanes;
>
> regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
> if (!regs)
> @@ -883,6 +895,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
> return pcie->num_clks;
> }
>
> + ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
> + if (ret == 0) {
> + if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
> + dev_warn(dev, "Invalid num-lanes, using controller defaults\n");
> + else
> + pcie->num_lanes = num_lanes;
> + }
> +
> return 0;
> }
>
> --
> 2.46.1
>
On Tue, 2024-11-05 at 19:24 -0600, Bjorn Helgaas wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> On Mon, Nov 04, 2024 at 12:49:35PM +0100, AngeloGioacchino Del Regno
> wrote:
> > Add support for restricting the port's link width by specifying
> > the num-lanes devicetree property in the PCIe node.
> >
> > The setting is done in the GEN_SETTINGS register (in the driver
> > named as PCIE_SETTING_REG), where each set bit in [11:8] activates
> > a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2).
>
> I guess GEN_SETTINGS doesn't correspond to a register defined by the
> PCIe spec, right? The only thing in the spec that looks similar is
> the Target Link Width in the Device Control 3 register, but the bit
> position doesn't look like this PCIE_SETTING_LINK_WIDTH mask:
Hi Bjorn,
The "GEN_SETTINGS" and "LINK_WIDTH" settings will be reflected in the
Max Link Speed and Maximum Link Width fields in the PCIe Link
Capabilities Register.
However, these registers have slight differences in hardware design:
The Max Link Speed shown in the Link Capabilities Register can be
directly changed by the "GEN_SETTINGS" register, even if the hardware
cannot support such a high speed. On the other hand, when we set the
"LINK_WIDTH", it will compare with the maximum width that the hardware
actually supports and choose the smaller one.
Thanks.
>
> > #define PCIE_SETTING_REG 0x80
> > +#define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8)
> > #define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12)
> > #define PCIE_PCI_IDS_1 0x9c
> > #define PCI_CLASS(class) (class << 8)
> > @@ -168,6 +169,7 @@ struct mtk_msi_set {
> > * @clks: PCIe clocks
> > * @num_clks: PCIe clocks count for this port
> > * @max_link_speed: Maximum link speed (PCIe Gen) for this port
> > + * @num_lanes: Number of PCIe lanes for this port
> > * @irq: PCIe controller interrupt number
> > * @saved_irq_state: IRQ enable state saved at suspend time
> > * @irq_lock: lock protecting IRQ register access
> > @@ -189,6 +191,7 @@ struct mtk_gen3_pcie {
> > struct clk_bulk_data *clks;
> > int num_clks;
> > u8 max_link_speed;
> > + u8 num_lanes;
> >
> > int irq;
> > u32 saved_irq_state;
> > @@ -401,6 +404,14 @@ static int mtk_pcie_startup_port(struct
> > mtk_gen3_pcie *pcie)
> > val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT,
> > GENMASK(pcie-
> > >max_link_speed - 2, 0));
> > }
> > + if (pcie->num_lanes) {
> > + val &= ~PCIE_SETTING_LINK_WIDTH;
> > +
> > + /* Zero means one lane, each bit activates
> > x2/x4/x8/x16 */
> > + if (pcie->num_lanes > 1)
> > + val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH,
> > + GENMASK(fls(pcie->num_lanes
> > >> 2), 0));
> > + };
> > writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
> >
> > /* Set Link Control 2 (LNKCTL2) speed restriction, if any */
> > @@ -838,6 +849,7 @@ static int mtk_pcie_parse_port(struct
> > mtk_gen3_pcie *pcie)
> > struct device *dev = pcie->dev;
> > struct platform_device *pdev = to_platform_device(dev);
> > struct resource *regs;
> > + u32 num_lanes;
> >
> > regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > "pcie-mac");
> > if (!regs)
> > @@ -883,6 +895,14 @@ static int mtk_pcie_parse_port(struct
> > mtk_gen3_pcie *pcie)
> > return pcie->num_clks;
> > }
> >
> > + ret = of_property_read_u32(dev->of_node, "num-lanes",
> > &num_lanes);
> > + if (ret == 0) {
> > + if (num_lanes == 0 || num_lanes > 16 || (num_lanes !=
> > 1 && num_lanes % 2))
> > + dev_warn(dev, "Invalid num-lanes, using
> > controller defaults\n");
> > + else
> > + pcie->num_lanes = num_lanes;
> > + }
> > +
> > return 0;
> > }
> >
> > --
> > 2.46.1
> >
Hello,
> + ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
> + if (ret == 0) {
> + if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
> + dev_warn(dev, "Invalid num-lanes, using controller defaults\n");
> + else
> + pcie->num_lanes = num_lanes;
> + }
> +
> return 0;
> }
If you were to handle non-zero return value as an error here, perhaps the
property has not been set, then we could reduce the indentation here.
Something like this, perhaps?
ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
if (ret) {
dev_err(dev, "Failed to read num-lanes: %d\n", ret);
return ret;
}
if (!num_lanes || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
dev_warn(dev, "Invalid num-lanes, using controller defaults\n");
else
pcie->num_lanes = num_lanes;
Does this make sense here? Thoughts?
Krzysztof
Il 04/11/24 14:20, Krzysztof Wilczyński ha scritto:
>
> Hello,
>
>> + ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
>> + if (ret == 0) {
>> + if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
>> + dev_warn(dev, "Invalid num-lanes, using controller defaults\n");
>> + else
>> + pcie->num_lanes = num_lanes;
>> + }
>> +
>> return 0;
>> }
>
> If you were to handle non-zero return value as an error here, perhaps the
> property has not been set, then we could reduce the indentation here.
>
> Something like this, perhaps?
>
> ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
> if (ret) {
> dev_err(dev, "Failed to read num-lanes: %d\n", ret);
> return ret;
> }
>
> if (!num_lanes || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
> dev_warn(dev, "Invalid num-lanes, using controller defaults\n");
> else
> pcie->num_lanes = num_lanes;
>
> Does this make sense here? Thoughts?
>
> Krzysztof
Sorry I've just seen this email.
There's a problem here: this property has to be optional - and if you change that
to return like that, you're breaking compatibility with older device trees, which
are not specifying any "num-lanes" property.
Please remember that of_property_read_u32() returns:
- 0 on success
- -EINVAL if the property does not exist
- -ENODATA or -EOVERFLOW
Please either keep the error checking like I wrote, or alternatively you can do..
ret = of_property_read_u32(...)
if (ret != -EINVAL) {
dev_err(dev, "Failed to read num-lanes: %d\n", ret);
return ret;
} else {
if (num_lanes == 0 || ..... etc etc)
dev_warn()
else
pcie->num_lanes = num_lanes
}
Cheers,
Angelo
Hello, > > Does this make sense here? Thoughts? [...] > There's a problem here: this property has to be optional - and if you change that > to return like that, you're breaking compatibility with older device trees, which > are not specifying any "num-lanes" property. Makes sense. I will keep your version. Thank you! Krzysztof
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