From: Diogo Silva <diogompaissilva@gmail.com>

DP83848	datasheet (section 4.7.2) indicates that the reset pin should be
toggled after the clocks are running. Add the PHY_RST_AFTER_CLK_EN to
make sure that this indication is respected.

In my experience not having this flag enabled would lead to, on some
boots, the wrong MII mode being selected if the PHY was initialized on
the bootloader and was receiving data during Linux boot.

Signed-off-by: Diogo Silva <diogompaissilva@gmail.com>
---
 drivers/net/phy/dp83848.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/phy/dp83848.c b/drivers/net/phy/dp83848.c
index 937061acfc61..351411f0aa6f 100644
--- a/drivers/net/phy/dp83848.c
+++ b/drivers/net/phy/dp83848.c
@@ -147,6 +147,8 @@ MODULE_DEVICE_TABLE(mdio, dp83848_tbl);
 		/* IRQ related */				\
 		.config_intr	= dp83848_config_intr,		\
 		.handle_interrupt = dp83848_handle_interrupt,	\
+								\
+		.flags		= PHY_RST_AFTER_CLK_EN,		\
 	}
 
 static struct phy_driver dp83848_driver[] = {
-- 
2.46.0

On Sat, Nov 02, 2024 at 04:15:05PM +0100, Diogo Silva wrote:
> From: Diogo Silva <diogompaissilva@gmail.com>
> 
> DP83848	datasheet (section 4.7.2) indicates that the reset pin should be
> toggled after the clocks are running. Add the PHY_RST_AFTER_CLK_EN to
> make sure that this indication is respected.
> 
> In my experience not having this flag enabled would lead to, on some
> boots, the wrong MII mode being selected if the PHY was initialized on
> the bootloader and was receiving data during Linux boot.
> 
> Signed-off-by: Diogo Silva <diogompaissilva@gmail.com>

This should be merged to net.

Fixes: 34e45ad9378c ("net: phy: dp83848: Add TI DP83848 Ethernet PHY")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

On Sat, Nov 02, 2024 at 04:15:05PM +0100, Diogo Silva wrote:
> From: Diogo Silva <diogompaissilva@gmail.com>
> 
> DP83848	datasheet (section 4.7.2) indicates that the reset pin should be
> toggled after the clocks are running. Add the PHY_RST_AFTER_CLK_EN to
> make sure that this indication is respected.

Do you have the datasheets for the other three devices this driver
supports? Do they all require this flag?

	Andrew

Hi Andrew,

I assume "TI DP83848C" and "NS DP83848C" are the same device, just
rebranded after Texas Instruments acquired National Semiconductors.
For both TLK10X and DP83620, both their datasheets have the same power
up timing sequence as the DP83848C (as far as clock and reset goes)
[1][2].

Best regards,
Diogo Silva

[1] https://www.ti.com/lit/ds/symlink/tlk105.pdf (section 9.10.1 -
Power Up Timing)
[2] https://www.ti.com/lit/ds/symlink/dp83620.pdf (section 4.5 - Power
Up Timing)

On Sat, 2 Nov 2024 at 18:03, Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Sat, Nov 02, 2024 at 04:15:05PM +0100, Diogo Silva wrote:
> > From: Diogo Silva <diogompaissilva@gmail.com>
> >
> > DP83848       datasheet (section 4.7.2) indicates that the reset pin should be
> > toggled after the clocks are running. Add the PHY_RST_AFTER_CLK_EN to
> > make sure that this indication is respected.
>
> Do you have the datasheets for the other three devices this driver
> supports? Do they all require this flag?
>
>         Andrew