The 'UNIPHY' PCS block in the IPQ9574 SoC includes PCS and SerDes
functions. It supports different interface modes to enable Ethernet
MAC connections to different types of external PHYs/switch. It includes
PCS functions for 1Gbps and 2.5Gbps interface modes and XPCS functions
for 10Gbps interface modes. There are three UNIPHY (PCS) instances
in IPQ9574 SoC which provide PCS/XPCS functions to the six Ethernet
ports.
Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
---
.../bindings/net/pcs/qcom,ipq9574-pcs.yaml | 230 +++++++++++++++++++++
include/dt-bindings/net/pcs-qcom-ipq.h | 15 ++
2 files changed, 245 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
new file mode 100644
index 000000000000..a33873c7ad73
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
@@ -0,0 +1,230 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/qcom,ipq9574-pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ethernet PCS for Qualcomm IPQ SoC
+
+maintainers:
+ - Lei Wei <quic_leiwei@quicinc.com>
+
+description:
+ The UNIPHY hardware blocks in the Qualcomm IPQ SoC include PCS and SerDes
+ functions. They enable connectivity between the Ethernet MAC inside the
+ PPE (packet processing engine) and external Ethernet PHY/switch. There are
+ three UNIPHY instances in IPQ9574 SoC which provide PCS functions to the
+ six Ethernet ports.
+
+ For SGMII (1Gbps PHY) or 2500BASE-X (2.5Gbps PHY) interface modes, the PCS
+ function is enabled by using the PCS block inside UNIPHY. For USXGMII (10Gbps
+ PHY), the XPCS block in UNIPHY is used.
+
+ The SerDes provides 125M (1Gbps mode) or 312.5M (2.5Gbps and 10Gbps modes)
+ RX and TX clocks to the NSSCC (Networking Sub System Clock Controller). The
+ NSSCC divides these clocks and generates the MII RX and TX clocks to each
+ of the MII interfaces between the PCS and MAC, as per the link speeds and
+ interface modes.
+
+ Different IPQ SoC may support different number of UNIPHYs (PCSes) since the
+ number of ports and their capabilities can be different between these SoCs
+
+ Below diagram depicts the UNIPHY (PCS) connections for an IPQ9574 SoC based
+ board. In this example, the first PCS0 has four GMIIs/XGMIIs, which can connect
+ with four MACs to support QSGMII (4 x 1Gbps) or 10G_QXGMII (4 x 2.5Gbps)
+ interface modes.
+
+ - +-------+ +---------+ +-------------------------+
+ +---------+CMN PLL| | GCC | | NSSCC (Divider) |
+ | +----+--+ +----+----+ +--+-------+--------------+
+ | | | ^ |
+ | 31.25M | SYS/AHB|clk RX/TX|clk +------------+
+ | ref clk| | | | |
+ | | v | MII RX|TX clk MAC| RX/TX clk
+ |25/50M +--+---------+----------+-------+---+ +-+---------+
+ |ref clk | | +----------------+ | | | | PPE |
+ v | | | UNIPHY0 V | | V |
+ +-------+ | v | +-----------+ (X)GMII| | |
+ | | | +---+---+ | |--------|------|-- MAC0 |
+ | | | | | | | (X)GMII| | |
+ | Quad | | |SerDes | | PCS/XPCS |--------|------|-- MAC1 |
+ | +<----+ | | | | (X)GMII| | |
+ |(X)GPHY| | | | | |--------|------|-- MAC2 |
+ | | | | | | | (X)GMII| | |
+ | | | +-------+ | |--------|------|-- MAC3 |
+ +-------+ | | | | | |
+ | +-----------+ | | |
+ +-----------------------------------+ | |
+ +--+---------+----------+-------+---+ | |
+ +-------+ | UNIPHY1 | | |
+ | | | +-----------+ | | |
+ |(X)GPHY| | +-------+ | | (X)GMII| | |
+ | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC4 |
+ | | | | | | | | | |
+ +-------+ | +-------+ | | | | |
+ | +-----------+ | | |
+ +-----------------------------------+ | |
+ +--+---------+----------+-------+---+ | |
+ +-------+ | UNIPHY2 | | |
+ | | | +-----------+ | | |
+ |(X)GPHY| | +-------+ | | (X)GMII| | |
+ | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC5 |
+ | | | | | | | | | |
+ +-------+ | +-------+ | | | | |
+ | +-----------+ | | |
+ +-----------------------------------+ +-----------+
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq9574-pcs
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ clocks:
+ items:
+ - description: system clock
+ - description: AHB clock needed for register interface access
+
+ clock-names:
+ items:
+ - const: sys
+ - const: ahb
+
+ '#clock-cells':
+ const: 1
+ description: See include/dt-bindings/net/pcs-qcom-ipq.h for constants
+
+patternProperties:
+ "^pcs-mii@[0-4]$":
+ type: object
+ description: PCS MII interface.
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 4
+ description: MII index
+
+ clocks:
+ items:
+ - description: PCS MII RX clock
+ - description: PCS MII TX clock
+
+ clock-names:
+ items:
+ - const: mii_rx
+ - const: mii_tx
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+
+ pcs0: ethernet-pcs@7a00000 {
+ compatible = "qcom,ipq9574-pcs";
+ reg = <0x7a00000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_UNIPHY0_SYS_CLK>,
+ <&gcc GCC_UNIPHY0_AHB_CLK>;
+ clock-names = "sys",
+ "ahb";
+ #clock-cells = <1>;
+
+ pcs0_mii0: pcs-mii@0 {
+ reg = <0>;
+ clocks = <&nsscc 116>,
+ <&nsscc 117>;
+ clock-names = "mii_rx",
+ "mii_tx";
+ };
+
+ pcs0_mii1: pcs-mii@1 {
+ reg = <1>;
+ clocks = <&nsscc 118>,
+ <&nsscc 119>;
+ clock-names = "mii_rx",
+ "mii_tx";
+ };
+
+ pcs0_mii2: pcs-mii@2 {
+ reg = <2>;
+ clocks = <&nsscc 120>,
+ <&nsscc 121>;
+ clock-names = "mii_rx",
+ "mii_tx";
+ };
+
+ pcs0_mii3: pcs-mii@3 {
+ reg = <3>;
+ clocks = <&nsscc 122>,
+ <&nsscc 123>;
+ clock-names = "mii_rx",
+ "mii_tx";
+ };
+ };
+
+ pcs1: ethernet-pcs@7a10000 {
+ compatible = "qcom,ipq9574-pcs";
+ reg = <0x7a10000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
+ <&gcc GCC_UNIPHY1_AHB_CLK>;
+ clock-names = "sys",
+ "ahb";
+ #clock-cells = <1>;
+
+ pcs1_mii0: pcs-mii@0 {
+ reg = <0>;
+ clocks = <&nsscc 124>,
+ <&nsscc 125>;
+ clock-names = "mii_rx",
+ "mii_tx";
+ };
+ };
+
+ pcs2: ethernet-pcs@7a20000 {
+ compatible = "qcom,ipq9574-pcs";
+ reg = <0x7a20000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_UNIPHY2_SYS_CLK>,
+ <&gcc GCC_UNIPHY2_AHB_CLK>;
+ clock-names = "sys",
+ "ahb";
+ #clock-cells = <1>;
+
+ pcs2_mii0: pcs-mii@0 {
+ reg = <0>;
+ clocks = <&nsscc 126>,
+ <&nsscc 127>;
+ clock-names = "mii_rx",
+ "mii_tx";
+ };
+ };
diff --git a/include/dt-bindings/net/pcs-qcom-ipq.h b/include/dt-bindings/net/pcs-qcom-ipq.h
new file mode 100644
index 000000000000..8d9124ffd75d
--- /dev/null
+++ b/include/dt-bindings/net/pcs-qcom-ipq.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Device Tree constants for the Qualcomm IPQ PCS
+ */
+
+#ifndef _DT_BINDINGS_PCS_QCOM_IPQ_H
+#define _DT_BINDINGS_PCS_QCOM_IPQ_H
+
+/* The RX and TX clocks which are provided from the SerDes to NSSCC. */
+#define PCS_RX_CLK 0
+#define PCS_TX_CLK 1
+
+#endif /* _DT_BINDINGS_PCS_QCOM_IPQ_H */
--
2.34.1On Fri, Nov 01, 2024 at 06:32:49PM +0800, Lei Wei wrote:
> The 'UNIPHY' PCS block in the IPQ9574 SoC includes PCS and SerDes
> functions. It supports different interface modes to enable Ethernet
> MAC connections to different types of external PHYs/switch. It includes
> PCS functions for 1Gbps and 2.5Gbps interface modes and XPCS functions
> for 10Gbps interface modes. There are three UNIPHY (PCS) instances
> in IPQ9574 SoC which provide PCS/XPCS functions to the six Ethernet
> ports.
>
> Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
> ---
> .../bindings/net/pcs/qcom,ipq9574-pcs.yaml | 230 +++++++++++++++++++++
> include/dt-bindings/net/pcs-qcom-ipq.h | 15 ++
> 2 files changed, 245 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
> new file mode 100644
> index 000000000000..a33873c7ad73
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
> @@ -0,0 +1,230 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/pcs/qcom,ipq9574-pcs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ethernet PCS for Qualcomm IPQ SoC
s/IPQ/IPQ9574/
> +
> +maintainers:
> + - Lei Wei <quic_leiwei@quicinc.com>
...
> + const: 0
> +
> + clocks:
> + items:
> + - description: system clock
> + - description: AHB clock needed for register interface access
> +
> + clock-names:
> + items:
> + - const: sys
> + - const: ahb
> +
> + '#clock-cells':
Use consistent quotes, either ' or "
> + const: 1
> + description: See include/dt-bindings/net/pcs-qcom-ipq.h for constants
> +
> +patternProperties:
> + "^pcs-mii@[0-4]$":
> + type: object
> + description: PCS MII interface.
> +
> + properties:
> + reg:
> + minimum: 0
> + maximum: 4
> + description: MII index
> +
> + clocks:
> + items:
> + - description: PCS MII RX clock
> + - description: PCS MII TX clock
> +
> + clock-names:
> + items:
> + - const: mii_rx
rx
> + - const: mii_tx
tx
> +
> + required:
> + - reg
> + - clocks
> + - clock-names
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - '#address-cells'
> + - '#size-cells'
> + - clocks
> + - clock-names
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> +
> + pcs0: ethernet-pcs@7a00000 {
Drop unused labels here and further.
> + compatible = "qcom,ipq9574-pcs";
> + reg = <0x7a00000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&gcc GCC_UNIPHY0_SYS_CLK>,
> + <&gcc GCC_UNIPHY0_AHB_CLK>;
> + clock-names = "sys",
> + "ahb";
> + #clock-cells = <1>;
> +
> + pcs0_mii0: pcs-mii@0 {
> + reg = <0>;
> + clocks = <&nsscc 116>,
> + <&nsscc 117>;
> + clock-names = "mii_rx",
> + "mii_tx";
> + };
> +
> + pcs0_mii1: pcs-mii@1 {
> + reg = <1>;
> + clocks = <&nsscc 118>,
> + <&nsscc 119>;
> + clock-names = "mii_rx",
> + "mii_tx";
> + };
> +
> + pcs0_mii2: pcs-mii@2 {
> + reg = <2>;
> + clocks = <&nsscc 120>,
> + <&nsscc 121>;
> + clock-names = "mii_rx",
> + "mii_tx";
> + };
> +
> + pcs0_mii3: pcs-mii@3 {
> + reg = <3>;
> + clocks = <&nsscc 122>,
> + <&nsscc 123>;
> + clock-names = "mii_rx",
> + "mii_tx";
> + };
> + };
> +
> + pcs1: ethernet-pcs@7a10000 {
One example is enough, drop the rest.
> + compatible = "qcom,ipq9574-pcs";
> + reg = <0x7a10000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
> + <&gcc GCC_UNIPHY1_AHB_CLK>;
> + clock-names = "sys",
> + "ahb";
> + #clock-cells = <1>;
> +
> + pcs1_mii0: pcs-mii@0 {
> + reg = <0>;
> + clocks = <&nsscc 124>,
> + <&nsscc 125>;
> + clock-names = "mii_rx",
> + "mii_tx";
> + };
> + };
> +
> + pcs2: ethernet-pcs@7a20000 {
> + compatible = "qcom,ipq9574-pcs";
> + reg = <0x7a20000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&gcc GCC_UNIPHY2_SYS_CLK>,
> + <&gcc GCC_UNIPHY2_AHB_CLK>;
> + clock-names = "sys",
> + "ahb";
> + #clock-cells = <1>;
> +
> + pcs2_mii0: pcs-mii@0 {
> + reg = <0>;
> + clocks = <&nsscc 126>,
> + <&nsscc 127>;
> + clock-names = "mii_rx",
> + "mii_tx";
> + };
> + };
> diff --git a/include/dt-bindings/net/pcs-qcom-ipq.h b/include/dt-bindings/net/pcs-qcom-ipq.h
> new file mode 100644
> index 000000000000..8d9124ffd75d
> --- /dev/null
> +++ b/include/dt-bindings/net/pcs-qcom-ipq.h
Filename matching exactly binding filename.
Best regards,
Krzysztof
On 11/2/2024 9:34 PM, Krzysztof Kozlowski wrote:
> On Fri, Nov 01, 2024 at 06:32:49PM +0800, Lei Wei wrote:
>> The 'UNIPHY' PCS block in the IPQ9574 SoC includes PCS and SerDes
>> functions. It supports different interface modes to enable Ethernet
>> MAC connections to different types of external PHYs/switch. It includes
>> PCS functions for 1Gbps and 2.5Gbps interface modes and XPCS functions
>> for 10Gbps interface modes. There are three UNIPHY (PCS) instances
>> in IPQ9574 SoC which provide PCS/XPCS functions to the six Ethernet
>> ports.
>>
>> Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
>> ---
>> .../bindings/net/pcs/qcom,ipq9574-pcs.yaml | 230 +++++++++++++++++++++
>> include/dt-bindings/net/pcs-qcom-ipq.h | 15 ++
>> 2 files changed, 245 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
>> new file mode 100644
>> index 000000000000..a33873c7ad73
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
>> @@ -0,0 +1,230 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/net/pcs/qcom,ipq9574-pcs.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Ethernet PCS for Qualcomm IPQ SoC
>
> s/IPQ/IPQ9574/
>
OK, will update.
>> +
>> +maintainers:
>> + - Lei Wei <quic_leiwei@quicinc.com>
>
> ...
>
>> + const: 0
>> +
>> + clocks:
>> + items:
>> + - description: system clock
>> + - description: AHB clock needed for register interface access
>> +
>> + clock-names:
>> + items:
>> + - const: sys
>> + - const: ahb
>> +
>> + '#clock-cells':
>
> Use consistent quotes, either ' or "
>
OK, will use single quotes ' everywhere.
>> + const: 1
>> + description: See include/dt-bindings/net/pcs-qcom-ipq.h for constants
>> +
>> +patternProperties:
>> + "^pcs-mii@[0-4]$":
>> + type: object
>> + description: PCS MII interface.
>> +
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 4
>> + description: MII index
>> +
>> + clocks:
>> + items:
>> + - description: PCS MII RX clock
>> + - description: PCS MII TX clock
>> +
>> + clock-names:
>> + items:
>> + - const: mii_rx
>
> rx
>
OK.
>> + - const: mii_tx
>
> tx
OK.
>
>> +
>> + required:
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> + additionalProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - '#address-cells'
>> + - '#size-cells'
>> + - clocks
>> + - clock-names
>> + - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> +
>> + pcs0: ethernet-pcs@7a00000 {
>
> Drop unused labels here and further.
>
OK, will drop the unused labels "pcs0" and "pcs0_miiX".
>> + compatible = "qcom,ipq9574-pcs";
>> + reg = <0x7a00000 0x10000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&gcc GCC_UNIPHY0_SYS_CLK>,
>> + <&gcc GCC_UNIPHY0_AHB_CLK>;
>> + clock-names = "sys",
>> + "ahb";
>> + #clock-cells = <1>;
>> +
>> + pcs0_mii0: pcs-mii@0 {
>> + reg = <0>;
>> + clocks = <&nsscc 116>,
>> + <&nsscc 117>;
>> + clock-names = "mii_rx",
>> + "mii_tx";
>> + };
>> +
>> + pcs0_mii1: pcs-mii@1 {
>> + reg = <1>;
>> + clocks = <&nsscc 118>,
>> + <&nsscc 119>;
>> + clock-names = "mii_rx",
>> + "mii_tx";
>> + };
>> +
>> + pcs0_mii2: pcs-mii@2 {
>> + reg = <2>;
>> + clocks = <&nsscc 120>,
>> + <&nsscc 121>;
>> + clock-names = "mii_rx",
>> + "mii_tx";
>> + };
>> +
>> + pcs0_mii3: pcs-mii@3 {
>> + reg = <3>;
>> + clocks = <&nsscc 122>,
>> + <&nsscc 123>;
>> + clock-names = "mii_rx",
>> + "mii_tx";
>> + };
>> + };
>> +
>> + pcs1: ethernet-pcs@7a10000 {
>
> One example is enough, drop the rest.
>
OK.
>> + compatible = "qcom,ipq9574-pcs";
>> + reg = <0x7a10000 0x10000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
>> + <&gcc GCC_UNIPHY1_AHB_CLK>;
>> + clock-names = "sys",
>> + "ahb";
>> + #clock-cells = <1>;
>> +
>> + pcs1_mii0: pcs-mii@0 {
>> + reg = <0>;
>> + clocks = <&nsscc 124>,
>> + <&nsscc 125>;
>> + clock-names = "mii_rx",
>> + "mii_tx";
>> + };
>> + };
>> +
>> + pcs2: ethernet-pcs@7a20000 {
>> + compatible = "qcom,ipq9574-pcs";
>> + reg = <0x7a20000 0x10000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&gcc GCC_UNIPHY2_SYS_CLK>,
>> + <&gcc GCC_UNIPHY2_AHB_CLK>;
>> + clock-names = "sys",
>> + "ahb";
>> + #clock-cells = <1>;
>> +
>> + pcs2_mii0: pcs-mii@0 {
>> + reg = <0>;
>> + clocks = <&nsscc 126>,
>> + <&nsscc 127>;
>> + clock-names = "mii_rx",
>> + "mii_tx";
>> + };
>> + };
>> diff --git a/include/dt-bindings/net/pcs-qcom-ipq.h b/include/dt-bindings/net/pcs-qcom-ipq.h
>> new file mode 100644
>> index 000000000000..8d9124ffd75d
>> --- /dev/null
>> +++ b/include/dt-bindings/net/pcs-qcom-ipq.h
>
> Filename matching exactly binding filename.
>
OK.
> Best regards,
> Krzysztof
>
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