The Agilex5 clock tree is compatible to the existing s10 drivers.
Therefore the pll,gate and periph drivers can be reused and only the
main clock tree is added.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
Teh Wen Ping (2):
dt-bindings: clk: agilex5: Add Agilex5 clock bindings
clk: socfpga: Add clock driver for Agilex5
drivers/clk/socfpga/Kconfig | 4 +-
drivers/clk/socfpga/Makefile | 2 +-
drivers/clk/socfpga/clk-agilex5.c | 847 ++++++++++++++++++++++++++++++
drivers/clk/socfpga/clk-pll-s10.c | 48 ++
drivers/clk/socfpga/stratix10-clk.h | 2 +
include/dt-bindings/clock/agilex5-clock.h | 100 ++++
6 files changed, 1000 insertions(+), 3 deletions(-)
---
base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc
change-id: 20241030-v6-12-topic-socfpga-agilex5-clk-7bea43c8b9b5
Best regards,
--
Steffen Trumtrar <s.trumtrar@pengutronix.de>