From: Gregory CLEMENT <gregory.clement@bootlin.com>

Some CM3.5 reports show that Hardware Cache Initialization is
complete, but in reality it's not the case. They also incorrectly
indicate that Hardware Cache Initialization is supported. This
optional property allows warning about this broken feature that cannot
be detected at runtime.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 Documentation/devicetree/bindings/mips/cpus.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
index a85137add668..57e93c07ab1b 100644
--- a/Documentation/devicetree/bindings/mips/cpus.yaml
+++ b/Documentation/devicetree/bindings/mips/cpus.yaml
@@ -47,6 +47,12 @@ properties:
   clocks:
     maxItems: 1
 
+  cm3-l2-config-hci-broken:
+    type: boolean
+    description:
+      If present, indicates that the HCI (Hardware Cache Initialization)
+      information for the L2 cache in multi-cluster configuration is broken.
+
   device_type: true
 
 allOf:
-- 
2.25.1

On Mon, Oct 28, 2024 at 06:59:32PM +0100, Aleksandar Rikalo wrote:
> From: Gregory CLEMENT <gregory.clement@bootlin.com>
> 
> Some CM3.5 reports show that Hardware Cache Initialization is
> complete, but in reality it's not the case. They also incorrectly
> indicate that Hardware Cache Initialization is supported. This
> optional property allows warning about this broken feature that cannot
> be detected at runtime.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com>
> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
>  Documentation/devicetree/bindings/mips/cpus.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

I cannot find this patch in v6, nothing in changelog explaining what
happened here.

> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
> index a85137add668..57e93c07ab1b 100644
> --- a/Documentation/devicetree/bindings/mips/cpus.yaml
> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
> @@ -47,6 +47,12 @@ properties:
>    clocks:
>      maxItems: 1
>  
> +  cm3-l2-config-hci-broken:

Are these names - cm3, l2, hci - obvious and known in MIPS? HCI usually
means something else - see drivers/bluetooth/ and drivers/nfc/

Is this property applicable for all MIPS vendors? There is no vendor
prefix here, so this is generic for this architecture, right?

Best regards,
Krzysztof

On Tue, Oct 29, 2024 at 8:03 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:

> > diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
> > index a85137add668..57e93c07ab1b 100644
> > --- a/Documentation/devicetree/bindings/mips/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
> > @@ -47,6 +47,12 @@ properties:
> >    clocks:
> >      maxItems: 1
> >
> > +  cm3-l2-config-hci-broken:
>
> Are these names - cm3, l2, hci - obvious and known in MIPS? HCI usually
> means something else - see drivers/bluetooth/ and drivers/nfc/

I would say yes. At least the name "CM3" (Coherence Manager 3) is
common knowledge.
L2 HCI (L2 Hardware Cache Initialization) is a feature of CM3 that is
non-functional on some systems.

> Is this property applicable for all MIPS vendors? There is no vendor
> prefix here, so this is generic for this architecture, right?

I'm honestly not sure if this is something that only one vendor will use.
Theoretically, there could be more. Perhaps Gregory CLEMENT can give a
more precise answer.

Best Regards,
Aleksandar

Hi,

> On Tue, Oct 29, 2024 at 8:03 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
>> > diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
>> > index a85137add668..57e93c07ab1b 100644
>> > --- a/Documentation/devicetree/bindings/mips/cpus.yaml
>> > +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
>> > @@ -47,6 +47,12 @@ properties:
>> >    clocks:
>> >      maxItems: 1
>> >
>> > +  cm3-l2-config-hci-broken:
>>
>> Are these names - cm3, l2, hci - obvious and known in MIPS? HCI usually
>> means something else - see drivers/bluetooth/ and drivers/nfc/
>
> I would say yes. At least the name "CM3" (Coherence Manager 3) is
> common knowledge.
> L2 HCI (L2 Hardware Cache Initialization) is a feature of CM3 that is
> non-functional on some systems.
>
>> Is this property applicable for all MIPS vendors? There is no vendor
>> prefix here, so this is generic for this architecture, right?
>
> I'm honestly not sure if this is something that only one vendor will use.
> Theoretically, there could be more. Perhaps Gregory CLEMENT can give a
> more precise answer.

All I know is that this property is needed because of an issue in this
CPU designed by Imagination. So, to my knowledge, it is present at least
on some Imagination CPUs, but since it is an issue, I think any other
MIPS designer could encounter the same problem.

Gregory

>
> Best Regards,
> Aleksandar

-- 
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com