.../devicetree/bindings/mips/cpus.yaml | 6 + arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 1 + arch/mips/include/asm/mips-cm.h | 18 ++ arch/mips/include/asm/smp-cps.h | 7 +- arch/mips/kernel/asm-offsets.c | 3 + arch/mips/kernel/cps-vec.S | 19 +- arch/mips/kernel/mips-cm.c | 4 +- arch/mips/kernel/pm-cps.c | 35 +- arch/mips/kernel/smp-cps.c | 305 +++++++++++++++--- drivers/clocksource/mips-gic-timer.c | 45 ++- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-mips-gic.c | 269 ++++++++++++--- 12 files changed, 599 insertions(+), 114 deletions(-)
Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu.
Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and
1 cluster/4 VPU configurations.
v8:
- irqchip: mips-gic: Handle case with cluster without CPU cores.
- Add Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> for the entire series.
- Re-base onto the master branch, with no functionality impact.
v7:
- Add fixes for specific CM3.5 which is used in EyeQ6H SoCs, suggested by Gregory Clement.
- Re-base onto the master branch, with no functionality impact.
v6:
- Re-base onto the master branch, with no functionality impact.
- Correct the issue reported by the kernel test robot.
v5:
- Drop FDC related changes (patches 12, 13, and 14).
- Apply changes suggested by Thomas Gleixner (patches 3 and 4).
- Add #include <linux/cpumask.h> to patch 1, suggested by Thomas Bogendoerfer.
- Add Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> for the patch 08/11.
- Add Tested-by: Serge Semin <fancer.lancer@gmail.com> for the entire series.
- Correct some commit messages.
v4:
- Re-base onto the master branch, with no functionality impact.
- Refactor MIPS FDC driver in the context of multicluster support.
v3:
- Add Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> for the patch 02/12.
- Add the changes requested by Marc Zyngier for the 3/12 patch.
- Remove the patch 11/12 (a consequence of a discussion between Jiaxun Yang
and Marc Zyngier.
- Re-base onto the master branch, with no functionality impact.
v2:
- Apply correct Signed-off-by to avoid confusion.
Chao-ying Fu (1):
irqchip/mips-gic: Setup defaults in each cluster
Gregory CLEMENT (4):
dt-bindings: mips: cpu: Add property for broken HCI information
MIPS: CPS: Support broken HCI for multicluster
MIPS: mobileye: dts: eyeq6h: Enable cluster support
irqchip: mips-gic: Handle case with cluster without CPU cores
Paul Burton (8):
irqchip/mips-gic: Introduce for_each_online_cpu_gic()
irqchip/mips-gic: Support multi-cluster in for_each_online_cpu_gic()
irqchip/mips-gic: Multi-cluster support
clocksource: mips-gic-timer: Always use cluster 0 counter as
clocksource
clocksource: mips-gic-timer: Enable counter when CPUs start
MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core
MIPS: CPS: Introduce struct cluster_boot_config
MIPS: CPS: Boot CPUs in secondary clusters
.../devicetree/bindings/mips/cpus.yaml | 6 +
arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 1 +
arch/mips/include/asm/mips-cm.h | 18 ++
arch/mips/include/asm/smp-cps.h | 7 +-
arch/mips/kernel/asm-offsets.c | 3 +
arch/mips/kernel/cps-vec.S | 19 +-
arch/mips/kernel/mips-cm.c | 4 +-
arch/mips/kernel/pm-cps.c | 35 +-
arch/mips/kernel/smp-cps.c | 305 +++++++++++++++---
drivers/clocksource/mips-gic-timer.c | 45 ++-
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-mips-gic.c | 269 ++++++++++++---
12 files changed, 599 insertions(+), 114 deletions(-)
--
2.25.1
在2024年10月28日十月 下午5:59，Aleksandar Rikalo写道： > Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu. > Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and > 1 cluster/4 VPU configurations. For the whole series (despite pending dt-binding discussion): Reviewd-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> # Single cluster I6500 Thanks. - Jiaxun > > v8: > - irqchip: mips-gic: Handle case with cluster without CPU cores. > - Add Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> for the > entire series. > - Re-base onto the master branch, with no functionality impact. > > v7: > - Add fixes for specific CM3.5 which is used in EyeQ6H SoCs, suggested > by Gregory Clement. > - Re-base onto the master branch, with no functionality impact. > > v6: > - Re-base onto the master branch, with no functionality impact. > - Correct the issue reported by the kernel test robot. > > v5: > - Drop FDC related changes (patches 12, 13, and 14). > - Apply changes suggested by Thomas Gleixner (patches 3 and 4). > - Add #include <linux/cpumask.h> to patch 1, suggested by Thomas > Bogendoerfer. > - Add Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> for the > patch 08/11. > - Add Tested-by: Serge Semin <fancer.lancer@gmail.com> for the entire > series. > - Correct some commit messages. > > v4: > - Re-base onto the master branch, with no functionality impact. > - Refactor MIPS FDC driver in the context of multicluster support. > > v3: > - Add Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> for the patch 02/12. > - Add the changes requested by Marc Zyngier for the 3/12 patch. > - Remove the patch 11/12 (a consequence of a discussion between Jiaxun Yang > and Marc Zyngier. > - Re-base onto the master branch, with no functionality impact. > > v2: > - Apply correct Signed-off-by to avoid confusion. > > Chao-ying Fu (1): > irqchip/mips-gic: Setup defaults in each cluster > > Gregory CLEMENT (4): > dt-bindings: mips: cpu: Add property for broken HCI information > MIPS: CPS: Support broken HCI for multicluster > MIPS: mobileye: dts: eyeq6h: Enable cluster support > irqchip: mips-gic: Handle case with cluster without CPU cores > > Paul Burton (8): > irqchip/mips-gic: Introduce for_each_online_cpu_gic() > irqchip/mips-gic: Support multi-cluster in for_each_online_cpu_gic() > irqchip/mips-gic: Multi-cluster support > clocksource: mips-gic-timer: Always use cluster 0 counter as > clocksource > clocksource: mips-gic-timer: Enable counter when CPUs start > MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core > MIPS: CPS: Introduce struct cluster_boot_config > MIPS: CPS: Boot CPUs in secondary clusters > > .../devicetree/bindings/mips/cpus.yaml | 6 + > arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 1 + > arch/mips/include/asm/mips-cm.h | 18 ++ > arch/mips/include/asm/smp-cps.h | 7 +- > arch/mips/kernel/asm-offsets.c | 3 + > arch/mips/kernel/cps-vec.S | 19 +- > arch/mips/kernel/mips-cm.c | 4 +- > arch/mips/kernel/pm-cps.c | 35 +- > arch/mips/kernel/smp-cps.c | 305 +++++++++++++++--- > drivers/clocksource/mips-gic-timer.c | 45 ++- > drivers/irqchip/Kconfig | 1 + > drivers/irqchip/irq-mips-gic.c | 269 ++++++++++++--- > 12 files changed, 599 insertions(+), 114 deletions(-) > > -- > 2.25.1 -- - Jiaxun
On Wed, 30 Oct 2024, Jiaxun Yang wrote: > Reviewd-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Typo here. Maciej
Hello Aleksandar, > Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu. > Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and > 1 cluster/4 VPU configurations. I tested your series on top of v6.13, with some patches already merged. Only the patch "[PATCH v8 09/13] MIPS: CPS: Boot CPUs in secondary clusters" encountered a merge issue. You can review the fixed version I created as an attachment. With the v2 series I sent a few days ago, cluster support continued to work on EyeQ5 and EyeQ6. However, for specific needs requiring support of EyeQ6, I will send a new version that takes into account the feedback received. Gregory > > v8: > - irqchip: mips-gic: Handle case with cluster without CPU cores. > - Add Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> for the entire series. > - Re-base onto the master branch, with no functionality impact. > > v7: > - Add fixes for specific CM3.5 which is used in EyeQ6H SoCs, suggested by Gregory Clement. > - Re-base onto the master branch, with no functionality impact. > > v6: > - Re-base onto the master branch, with no functionality impact. > - Correct the issue reported by the kernel test robot. > > v5: > - Drop FDC related changes (patches 12, 13, and 14). > - Apply changes suggested by Thomas Gleixner (patches 3 and 4). > - Add #include <linux/cpumask.h> to patch 1, suggested by Thomas Bogendoerfer. > - Add Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> for the patch 08/11. > - Add Tested-by: Serge Semin <fancer.lancer@gmail.com> for the entire series. > - Correct some commit messages. > > v4: > - Re-base onto the master branch, with no functionality impact. > - Refactor MIPS FDC driver in the context of multicluster support. > > v3: > - Add Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> for the patch 02/12. > - Add the changes requested by Marc Zyngier for the 3/12 patch. > - Remove the patch 11/12 (a consequence of a discussion between Jiaxun Yang > and Marc Zyngier. > - Re-base onto the master branch, with no functionality impact. > > v2: > - Apply correct Signed-off-by to avoid confusion. > > Chao-ying Fu (1): > irqchip/mips-gic: Setup defaults in each cluster > > Gregory CLEMENT (4): > dt-bindings: mips: cpu: Add property for broken HCI information > MIPS: CPS: Support broken HCI for multicluster > MIPS: mobileye: dts: eyeq6h: Enable cluster support > irqchip: mips-gic: Handle case with cluster without CPU cores > > Paul Burton (8): > irqchip/mips-gic: Introduce for_each_online_cpu_gic() > irqchip/mips-gic: Support multi-cluster in for_each_online_cpu_gic() > irqchip/mips-gic: Multi-cluster support > clocksource: mips-gic-timer: Always use cluster 0 counter as > clocksource > clocksource: mips-gic-timer: Enable counter when CPUs start > MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core > MIPS: CPS: Introduce struct cluster_boot_config > MIPS: CPS: Boot CPUs in secondary clusters > > .../devicetree/bindings/mips/cpus.yaml | 6 + > arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 1 + > arch/mips/include/asm/mips-cm.h | 18 ++ > arch/mips/include/asm/smp-cps.h | 7 +- > arch/mips/kernel/asm-offsets.c | 3 + > arch/mips/kernel/cps-vec.S | 19 +- > arch/mips/kernel/mips-cm.c | 4 +- > arch/mips/kernel/pm-cps.c | 35 +- > arch/mips/kernel/smp-cps.c | 305 +++++++++++++++--- > drivers/clocksource/mips-gic-timer.c | 45 ++- > drivers/irqchip/Kconfig | 1 + > drivers/irqchip/irq-mips-gic.c | 269 ++++++++++++--- > 12 files changed, 599 insertions(+), 114 deletions(-) > > -- > 2.25.1 > -- Grégory CLEMENT, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
On Wed, Jan 22, 2025 at 4:06 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: > > Hello Aleksandar, > > > Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu. > > Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and > > 1 cluster/4 VPU configurations. > > I tested your series on top of v6.13, with some patches already > merged. Only the patch "[PATCH v8 09/13] MIPS: CPS: Boot CPUs in > secondary clusters" encountered a merge issue. You can review the fixed > version I created as an attachment. > > With the v2 series I sent a few days ago, cluster support continued to > work on EyeQ5 and EyeQ6. However, for specific needs requiring support > of EyeQ6, I will send a new version that takes into account the feedback > received. > > Gregory Hello Gregory, Thank you for your time. I agree with the change in the attachment. Will you send it to the list or should I do it as a v9 version of the series? Aleksandar
Hello Aleksandar, > On Wed, Jan 22, 2025 at 4:06 PM Gregory CLEMENT > <gregory.clement@bootlin.com> wrote: >> >> Hello Aleksandar, >> >> > Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu. >> > Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and >> > 1 cluster/4 VPU configurations. >> >> I tested your series on top of v6.13, with some patches already >> merged. Only the patch "[PATCH v8 09/13] MIPS: CPS: Boot CPUs in >> secondary clusters" encountered a merge issue. You can review the fixed >> version I created as an attachment. >> >> With the v2 series I sent a few days ago, cluster support continued to >> work on EyeQ5 and EyeQ6. However, for specific needs requiring support >> of EyeQ6, I will send a new version that takes into account the feedback >> received. >> >> Gregory > > Hello Gregory, > > Thank you for your time. > > I agree with the change in the attachment. Will you send it to the > list or should I do it as a v9 version of the series? I will let you send a v9 version. Feel free to merge my series [1] with yours, as some of my patches depend on your series. [1]: https://lore.kernel.org/lkml/20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com/ Thanks, Gregory -- Grégory CLEMENT, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Hello everyone, The new version, v9, is here: https://lore.kernel.org/linux-mips/20250129123250.711910-1-arikalo@gmail.com/ -- Aleksandar > Hello Aleksandar, > > > On Wed, Jan 22, 2025 at 4:06 PM Gregory CLEMENT > > <gregory.clement@bootlin.com> wrote: > >> > >> Hello Aleksandar, > >> > >> > Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu. > >> > Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and > >> > 1 cluster/4 VPU configurations. > >> > >> I tested your series on top of v6.13, with some patches already > >> merged. Only the patch "[PATCH v8 09/13] MIPS: CPS: Boot CPUs in > >> secondary clusters" encountered a merge issue. You can review the fixed > >> version I created as an attachment. > >> > >> With the v2 series I sent a few days ago, cluster support continued to > >> work on EyeQ5 and EyeQ6. However, for specific needs requiring support > >> of EyeQ6, I will send a new version that takes into account the feedback > >> received. > >> > >> Gregory > > > > Hello Gregory, > > > > Thank you for your time. > > > > I agree with the change in the attachment. Will you send it to the > > list or should I do it as a v9 version of the series? > > I will let you send a v9 version. Feel free to merge my series [1] with > yours, as some of my patches depend on your series. > > [1]: https://lore.kernel.org/lkml/20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com/ > > Thanks, > > Gregory > > -- > Grégory CLEMENT, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com
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