[v1] riscv: Add bfloat16 instruction support

[PATCH 0/3] riscv: Add bfloat16 instruction support

Inochi Amaoto posted 3 patches 4 weeks ago

Diff against v2
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Documentation/arch/riscv/hwprobe.rst          | 12 +++++
.../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++
arch/riscv/include/asm/hwcap.h                |  3 ++
arch/riscv/include/uapi/asm/hwprobe.h         |  3 ++
arch/riscv/kernel/cpufeature.c                |  3 ++
5 files changed, 66 insertions(+)

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[PATCH 0/3] riscv: Add bfloat16 instruction support

Posted by Inochi Amaoto 4 weeks ago

Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.

Inochi Amaoto (3):
  dt-bindings: riscv: add bfloat16 ISA extension description
  riscv: add ISA extension parsing for bfloat16 ISA extension
  riscv: hwprobe: export bfloat16 ISA extension

 Documentation/arch/riscv/hwprobe.rst          | 12 +++++
 .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++
 arch/riscv/include/asm/hwcap.h                |  3 ++
 arch/riscv/include/uapi/asm/hwprobe.h         |  3 ++
 arch/riscv/kernel/cpufeature.c                |  3 ++
 5 files changed, 66 insertions(+)

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2.47.0