[PATCH v3 2/2] clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug

Nick Hu posted 2 patches 4 weeks ago
[PATCH v3 2/2] clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug
Posted by Nick Hu 4 weeks ago
Stop the timer when the cpu is going to be offline otherwise the
timer interrupt may be pending while performing power-down.

Suggested-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/lkml/20240829033904.477200-3-nick.hu@sifive.com/T/#u
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 drivers/clocksource/timer-riscv.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 48ce50c5f5e6..166dee14e46b 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -127,6 +127,12 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
 static int riscv_timer_dying_cpu(unsigned int cpu)
 {
 	disable_percpu_irq(riscv_clock_event_irq);
+	/*
+	 * Stop the timer when the cpu is going to be offline otherwise
+	 * the timer interrupt may be pending while performing power-down.
+	 */
+	riscv_clock_event_stop();
+
 	return 0;
 }
 
-- 
2.34.1
Re: [PATCH v3 2/2] clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug
Posted by Daniel Lezcano 4 weeks ago
On 28/10/2024 04:39, Nick Hu wrote:
> Stop the timer when the cpu is going to be offline otherwise the
> timer interrupt may be pending while performing power-down.
> 
> Suggested-by: Anup Patel <anup@brainfault.org>
> Link: https://lore.kernel.org/lkml/20240829033904.477200-3-nick.hu@sifive.com/T/#u
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
>   drivers/clocksource/timer-riscv.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 48ce50c5f5e6..166dee14e46b 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -127,6 +127,12 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
>   static int riscv_timer_dying_cpu(unsigned int cpu)
>   {
>   	disable_percpu_irq(riscv_clock_event_irq);
> +	/*
> +	 * Stop the timer when the cpu is going to be offline otherwise
> +	 * the timer interrupt may be pending while performing power-down.
> +	 */
> +	riscv_clock_event_stop();
> +
>   	return 0;
>   }

Should it not be the opposite?

First stop the clock which clears the interrupt and then disable the irq?





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Re: [PATCH v3 2/2] clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug
Posted by Nick Hu 3 weeks, 6 days ago
Hi Daniel,

On Mon, Oct 28, 2024 at 5:44 PM Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
>
> On 28/10/2024 04:39, Nick Hu wrote:
> > Stop the timer when the cpu is going to be offline otherwise the
> > timer interrupt may be pending while performing power-down.
> >
> > Suggested-by: Anup Patel <anup@brainfault.org>
> > Link: https://lore.kernel.org/lkml/20240829033904.477200-3-nick.hu@sifive.com/T/#u
> > Signed-off-by: Nick Hu <nick.hu@sifive.com>
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> > ---
> >   drivers/clocksource/timer-riscv.c | 6 ++++++
> >   1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > index 48ce50c5f5e6..166dee14e46b 100644
> > --- a/drivers/clocksource/timer-riscv.c
> > +++ b/drivers/clocksource/timer-riscv.c
> > @@ -127,6 +127,12 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
> >   static int riscv_timer_dying_cpu(unsigned int cpu)
> >   {
> >       disable_percpu_irq(riscv_clock_event_irq);
> > +     /*
> > +      * Stop the timer when the cpu is going to be offline otherwise
> > +      * the timer interrupt may be pending while performing power-down.
> > +      */
> > +     riscv_clock_event_stop();
> > +
> >       return 0;
> >   }
>
> Should it not be the opposite?
>
> First stop the clock which clears the interrupt and then disable the irq?
>
SIE.STIE = 0 ->
Mtimer interrupt comes -> trap to m-mode -> raise STIP ->
stop the clock
Is the above case you are concerned about?

>
>
>
>
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