parent_bus_addr in struct of_range can indicate address information just
ahead of PCIe controller. Most system's bus fabric use 1:1 map between
input and output address. but some hardware like i.MX8QXP doesn't use 1:1
map. See below diagram:
┌─────────┐ ┌────────────┐
┌─────┐ │ │ IA: 0x8ff8_0000 │ │
│ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │
└─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │
CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │
0x7ff8_0000─┼───┘ │ │ │ │ │ │
│ │ │ │ │ │ │ PCI Addr
0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────►
│ │ │ │ │ 0
0x7000_0000─┼────────►├─────────┐ │ │ │
└─────────┘ │ └──────► CfgSpace ─┼────────────►
BUS Fabric │ │ │ 0
│ │ │
└──────────► MemSpace ─┼────────────►
IA: 0x8000_0000 │ │ 0x8000_0000
└────────────┘
bus@5f000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x80000000 0x0 0x70000000 0x10000000>;
pcie@5f010000 {
compatible = "fsl,imx8q-pcie";
reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>,
<0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>;
...
};
};
Term internal address (IA) here means the address just before PCIe
controller. After ATU use this IA instead CPU address, cpu_addr_fixup() can
be removed.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Chagne from v5 to v6
-add comments for of_property_read_reg().
Change from v4 to v5
- remove confused 0x5f00_0000 range in sample dts.
- reorder address at above diagram.
Change from v3 to v4
- none
Change from v2 to v3
- %s/cpu_untranslate_addr/parent_bus_addr/g
- update diagram.
- improve commit message.
Change from v1 to v2
- update because patch1 change get untranslate address method.
- add using_dtbus_info in case break back compatibility for exited platform.
---
drivers/pci/controller/dwc/pcie-designware-host.c | 49 +++++++++++++++++++++++
drivers/pci/controller/dwc/pcie-designware.h | 8 ++++
2 files changed, 57 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 3e41865c72904..a4f2578700eb3 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -418,6 +418,34 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
}
}
+static int dw_pcie_get_untranslate_addr(struct dw_pcie *pci, resource_size_t pci_addr,
+ resource_size_t *i_addr)
+{
+ struct device *dev = pci->dev;
+ struct device_node *np = dev->of_node;
+ struct of_range_parser parser;
+ struct of_range range;
+ int ret;
+
+ if (!pci->using_dtbus_info) {
+ *i_addr = pci_addr;
+ return 0;
+ }
+
+ ret = of_range_parser_init(&parser, np);
+ if (ret)
+ return ret;
+
+ for_each_of_pci_range(&parser, &range) {
+ if (pci_addr == range.bus_addr) {
+ *i_addr = range.parent_bus_addr;
+ break;
+ }
+ }
+
+ return 0;
+}
+
int dw_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -427,6 +455,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
struct resource_entry *win;
struct pci_host_bridge *bridge;
struct resource *res;
+ int index;
int ret;
raw_spin_lock_init(&pp->lock);
@@ -440,6 +469,20 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
pp->cfg0_size = resource_size(res);
pp->cfg0_base = res->start;
+ if (pci->using_dtbus_info) {
+ index = of_property_match_string(np, "reg-names", "config");
+ if (index < 0)
+ return -EINVAL;
+ /*
+ * Retrieve the parent bus address of PCI config space.
+ * If the parent bus ranges in the device tree provide
+ * the correct address conversion information, set
+ * 'using_dtbus_info' to true, The 'cpu_addr_fixup()'
+ * can be eliminated.
+ */
+ of_property_read_reg(np, index, &pp->cfg0_base, NULL);
+ }
+
pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
if (IS_ERR(pp->va_cfg0_base))
return PTR_ERR(pp->va_cfg0_base);
@@ -462,6 +505,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
pp->io_base = pci_pio_to_address(win->res->start);
}
+ if (dw_pcie_get_untranslate_addr(pci, pp->io_bus_addr, &pp->io_base))
+ return -ENODEV;
+
/* Set default bus ops */
bridge->ops = &dw_pcie_ops;
bridge->child_ops = &dw_child_pcie_ops;
@@ -733,6 +779,9 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
atu.cpu_addr = entry->res->start;
atu.pci_addr = entry->res->start - entry->offset;
+ if (dw_pcie_get_untranslate_addr(pci, atu.pci_addr, &atu.cpu_addr))
+ return -EINVAL;
+
/* Adjust iATU size if MSG TLP region was allocated before */
if (pp->msg_res && pp->msg_res->parent == entry->res)
atu.size = resource_size(entry->res) -
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 347ab74ac35aa..f8067393ad35a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -463,6 +463,14 @@ struct dw_pcie {
struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS];
struct gpio_desc *pe_rst;
bool suspended;
+ /*
+ * Use device tree 'ranges' property of bus node instead using
+ * cpu_addr_fixup(). Some old platform dts 'ranges' in bus node may not
+ * reflect real hardware's behavior. In case break these platform back
+ * compatibility, add below flags. Set it true if dts already correct
+ * indicate bus fabric address convert.
+ */
+ bool using_dtbus_info;
};
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
--
2.34.1
Hi Frank,
kernel test robot noticed the following build errors:
[auto build test ERROR on 9852d85ec9d492ebef56dc5f229416c925758edc]
url: https://github.com/intel-lab-lkp/linux/commits/Frank-Li/of-address-Add-parent_bus_addr-to-struct-of_pci_range/20241029-030935
base: 9852d85ec9d492ebef56dc5f229416c925758edc
patch link: https://lore.kernel.org/r/20241028-pci_fixup_addr-v6-2-ebebcd8fd4ff%40nxp.com
patch subject: [PATCH v6 2/7] PCI: dwc: Using parent_bus_addr in of_range to eliminate cpu_addr_fixup()
config: arm-defconfig (https://download.01.org/0day-ci/archive/20241029/202410291546.kvgEWJv7-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241029/202410291546.kvgEWJv7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/pci/controller/dwc/pcie-designware-host.c:782:55: error: incompatible pointer types passing 'u64 *' (aka 'unsigned long long *') to parameter of type 'resource_size_t *' (aka 'unsigned int *') [-Werror,-Wincompatible-pointer-types]
if (dw_pcie_get_untranslate_addr(pci, atu.pci_addr, &atu.cpu_addr))
^~~~~~~~~~~~~
drivers/pci/controller/dwc/pcie-designware-host.c:422:23: note: passing argument to parameter 'i_addr' here
resource_size_t *i_addr)
^
1 error generated.
vim +782 drivers/pci/controller/dwc/pcie-designware-host.c
745
746 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
747 {
748 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
749 struct dw_pcie_ob_atu_cfg atu = { 0 };
750 struct resource_entry *entry;
751 int i, ret;
752
753 /* Note the very first outbound ATU is used for CFG IOs */
754 if (!pci->num_ob_windows) {
755 dev_err(pci->dev, "No outbound iATU found\n");
756 return -EINVAL;
757 }
758
759 /*
760 * Ensure all out/inbound windows are disabled before proceeding with
761 * the MEM/IO (dma-)ranges setups.
762 */
763 for (i = 0; i < pci->num_ob_windows; i++)
764 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i);
765
766 for (i = 0; i < pci->num_ib_windows; i++)
767 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
768
769 i = 0;
770 resource_list_for_each_entry(entry, &pp->bridge->windows) {
771 if (resource_type(entry->res) != IORESOURCE_MEM)
772 continue;
773
774 if (pci->num_ob_windows <= ++i)
775 break;
776
777 atu.index = i;
778 atu.type = PCIE_ATU_TYPE_MEM;
779 atu.cpu_addr = entry->res->start;
780 atu.pci_addr = entry->res->start - entry->offset;
781
> 782 if (dw_pcie_get_untranslate_addr(pci, atu.pci_addr, &atu.cpu_addr))
783 return -EINVAL;
784
785 /* Adjust iATU size if MSG TLP region was allocated before */
786 if (pp->msg_res && pp->msg_res->parent == entry->res)
787 atu.size = resource_size(entry->res) -
788 resource_size(pp->msg_res);
789 else
790 atu.size = resource_size(entry->res);
791
792 ret = dw_pcie_prog_outbound_atu(pci, &atu);
793 if (ret) {
794 dev_err(pci->dev, "Failed to set MEM range %pr\n",
795 entry->res);
796 return ret;
797 }
798 }
799
800 if (pp->io_size) {
801 if (pci->num_ob_windows > ++i) {
802 atu.index = i;
803 atu.type = PCIE_ATU_TYPE_IO;
804 atu.cpu_addr = pp->io_base;
805 atu.pci_addr = pp->io_bus_addr;
806 atu.size = pp->io_size;
807
808 ret = dw_pcie_prog_outbound_atu(pci, &atu);
809 if (ret) {
810 dev_err(pci->dev, "Failed to set IO range %pr\n",
811 entry->res);
812 return ret;
813 }
814 } else {
815 pp->cfg0_io_shared = true;
816 }
817 }
818
819 if (pci->num_ob_windows <= i)
820 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
821 pci->num_ob_windows);
822
823 pp->msg_atu_index = i;
824
825 i = 0;
826 resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
827 if (resource_type(entry->res) != IORESOURCE_MEM)
828 continue;
829
830 if (pci->num_ib_windows <= i)
831 break;
832
833 ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM,
834 entry->res->start,
835 entry->res->start - entry->offset,
836 resource_size(entry->res));
837 if (ret) {
838 dev_err(pci->dev, "Failed to set DMA range %pr\n",
839 entry->res);
840 return ret;
841 }
842 }
843
844 if (pci->num_ib_windows <= i)
845 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
846 pci->num_ib_windows);
847
848 return 0;
849 }
850
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Frank,
kernel test robot noticed the following build errors:
[auto build test ERROR on 9852d85ec9d492ebef56dc5f229416c925758edc]
url: https://github.com/intel-lab-lkp/linux/commits/Frank-Li/of-address-Add-parent_bus_addr-to-struct-of_pci_range/20241029-030935
base: 9852d85ec9d492ebef56dc5f229416c925758edc
patch link: https://lore.kernel.org/r/20241028-pci_fixup_addr-v6-2-ebebcd8fd4ff%40nxp.com
patch subject: [PATCH v6 2/7] PCI: dwc: Using parent_bus_addr in of_range to eliminate cpu_addr_fixup()
config: openrisc-allyesconfig (https://download.01.org/0day-ci/archive/20241029/202410291248.Qc61mosK-lkp@intel.com/config)
compiler: or1k-linux-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241029/202410291248.Qc61mosK-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202410291248.Qc61mosK-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/pci/controller/dwc/pcie-designware-host.c: In function 'dw_pcie_iatu_setup':
>> drivers/pci/controller/dwc/pcie-designware-host.c:782:69: error: passing argument 3 of 'dw_pcie_get_untranslate_addr' from incompatible pointer type [-Wincompatible-pointer-types]
782 | if (dw_pcie_get_untranslate_addr(pci, atu.pci_addr, &atu.cpu_addr))
| ^~~~~~~~~~~~~
| |
| u64 * {aka long long unsigned int *}
drivers/pci/controller/dwc/pcie-designware-host.c:422:58: note: expected 'resource_size_t *' {aka 'unsigned int *'} but argument is of type 'u64 *' {aka 'long long unsigned int *'}
422 | resource_size_t *i_addr)
| ~~~~~~~~~~~~~~~~~^~~~~~
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for GET_FREE_REGION
Depends on [n]: SPARSEMEM [=n]
Selected by [y]:
- RESOURCE_KUNIT_TEST [=y] && RUNTIME_TESTING_MENU [=y] && KUNIT [=y]
vim +/dw_pcie_get_untranslate_addr +782 drivers/pci/controller/dwc/pcie-designware-host.c
745
746 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
747 {
748 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
749 struct dw_pcie_ob_atu_cfg atu = { 0 };
750 struct resource_entry *entry;
751 int i, ret;
752
753 /* Note the very first outbound ATU is used for CFG IOs */
754 if (!pci->num_ob_windows) {
755 dev_err(pci->dev, "No outbound iATU found\n");
756 return -EINVAL;
757 }
758
759 /*
760 * Ensure all out/inbound windows are disabled before proceeding with
761 * the MEM/IO (dma-)ranges setups.
762 */
763 for (i = 0; i < pci->num_ob_windows; i++)
764 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i);
765
766 for (i = 0; i < pci->num_ib_windows; i++)
767 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
768
769 i = 0;
770 resource_list_for_each_entry(entry, &pp->bridge->windows) {
771 if (resource_type(entry->res) != IORESOURCE_MEM)
772 continue;
773
774 if (pci->num_ob_windows <= ++i)
775 break;
776
777 atu.index = i;
778 atu.type = PCIE_ATU_TYPE_MEM;
779 atu.cpu_addr = entry->res->start;
780 atu.pci_addr = entry->res->start - entry->offset;
781
> 782 if (dw_pcie_get_untranslate_addr(pci, atu.pci_addr, &atu.cpu_addr))
783 return -EINVAL;
784
785 /* Adjust iATU size if MSG TLP region was allocated before */
786 if (pp->msg_res && pp->msg_res->parent == entry->res)
787 atu.size = resource_size(entry->res) -
788 resource_size(pp->msg_res);
789 else
790 atu.size = resource_size(entry->res);
791
792 ret = dw_pcie_prog_outbound_atu(pci, &atu);
793 if (ret) {
794 dev_err(pci->dev, "Failed to set MEM range %pr\n",
795 entry->res);
796 return ret;
797 }
798 }
799
800 if (pp->io_size) {
801 if (pci->num_ob_windows > ++i) {
802 atu.index = i;
803 atu.type = PCIE_ATU_TYPE_IO;
804 atu.cpu_addr = pp->io_base;
805 atu.pci_addr = pp->io_bus_addr;
806 atu.size = pp->io_size;
807
808 ret = dw_pcie_prog_outbound_atu(pci, &atu);
809 if (ret) {
810 dev_err(pci->dev, "Failed to set IO range %pr\n",
811 entry->res);
812 return ret;
813 }
814 } else {
815 pp->cfg0_io_shared = true;
816 }
817 }
818
819 if (pci->num_ob_windows <= i)
820 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
821 pci->num_ob_windows);
822
823 pp->msg_atu_index = i;
824
825 i = 0;
826 resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
827 if (resource_type(entry->res) != IORESOURCE_MEM)
828 continue;
829
830 if (pci->num_ib_windows <= i)
831 break;
832
833 ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM,
834 entry->res->start,
835 entry->res->start - entry->offset,
836 resource_size(entry->res));
837 if (ret) {
838 dev_err(pci->dev, "Failed to set DMA range %pr\n",
839 entry->res);
840 return ret;
841 }
842 }
843
844 if (pci->num_ib_windows <= i)
845 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
846 pci->num_ib_windows);
847
848 return 0;
849 }
850
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
© 2016 - 2024 Red Hat, Inc.