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[PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned

Dmitry Baryshkov posted 2 patches 1 year, 3 months ago
There is a newer version of this series
[PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned
Posted by Dmitry Baryshkov 1 year, 3 months ago 
From: Naman Jain <quic_namajain@quicinc.com>

Add logic for alignment of address for reading in qfprom driver to avoid
NOC error issues due to unaligned access. The problem manifests on the
SAR2130P platform, but in msm-5.x kernels the fix is applied
uncoditionally. Follow this approach and uncoditionally perform aligned
reads.

Fixes: 4ab11996b489 ("nvmem: qfprom: Add Qualcomm QFPROM support.")
Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/nvmem/qfprom.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
index 116a39e804c70b4a0374f8ea3ac6ba1dd612109d..cad319e7bfcf34c9b9ab15eb331efda822699cce 100644
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c
@@ -322,15 +322,28 @@ static int qfprom_reg_read(void *context,
 {
 	struct qfprom_priv *priv = context;
 	u8 *val = _val;
-	int i = 0, words = bytes;
+	int buf_start, buf_end, index, i = 0;
 	void __iomem *base = priv->qfpcorrected;
+	char *buffer = NULL;
+	u32 read_val;
 
 	if (read_raw_data && priv->qfpraw)
 		base = priv->qfpraw;
+	buf_start = ALIGN_DOWN(reg, 4);
+	buf_end = ALIGN(reg + bytes, 4);
+	buffer = kzalloc(buf_end - buf_start, GFP_KERNEL);
+	if (!buffer) {
+		pr_err("memory allocation failed in %s\n", __func__);
+		return -ENOMEM;
+	}
 
-	while (words--)
-		*val++ = readb(base + reg + i++);
+	for (index = buf_start; index < buf_end; index += 4, i += 4) {
+		read_val = readl_relaxed(base + index);
+		memcpy(buffer + i, &read_val, 4);
+	}
 
+	memcpy(val, buffer + reg % 4, bytes);
+	kfree(buffer);
 	return 0;
 }
 

-- 
2.39.5
Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned
Posted by Srinivas Kandagatla 1 year, 2 months ago 

On 26/10/2024 23:42, Dmitry Baryshkov wrote:
> From: Naman Jain <quic_namajain@quicinc.com>
> 
> Add logic for alignment of address for reading in qfprom driver to avoid
> NOC error issues due to unaligned access. The problem manifests on the
> SAR2130P platform, but in msm-5.x kernels the fix is applied

Is this only issue with SAR2130P?

> uncoditionally. Follow this approach and uncoditionally perform aligned
> reads.

If there is a need of having proper register alignment this should go as 
part of the nvmem_config->stride and word_size configuration and not in 
reg_read callbacks.


--srini

> 
> Fixes: 4ab11996b489 ("nvmem: qfprom: Add Qualcomm QFPROM support.")
> Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/nvmem/qfprom.c | 19 ++++++++++++++++---
>   1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
> index 116a39e804c70b4a0374f8ea3ac6ba1dd612109d..cad319e7bfcf34c9b9ab15eb331efda822699cce 100644
> --- a/drivers/nvmem/qfprom.c
> +++ b/drivers/nvmem/qfprom.c
> @@ -322,15 +322,28 @@ static int qfprom_reg_read(void *context,
>   {
>   	struct qfprom_priv *priv = context;
>   	u8 *val = _val;
> -	int i = 0, words = bytes;
> +	int buf_start, buf_end, index, i = 0;
>   	void __iomem *base = priv->qfpcorrected;
> +	char *buffer = NULL;
> +	u32 read_val;
>   
>   	if (read_raw_data && priv->qfpraw)
>   		base = priv->qfpraw;
> +	buf_start = ALIGN_DOWN(reg, 4);
> +	buf_end = ALIGN(reg + bytes, 4);
> +	buffer = kzalloc(buf_end - buf_start, GFP_KERNEL);
> +	if (!buffer) {
> +		pr_err("memory allocation failed in %s\n", __func__);
> +		return -ENOMEM;
> +	}
>   
> -	while (words--)
> -		*val++ = readb(base + reg + i++);
> +	for (index = buf_start; index < buf_end; index += 4, i += 4) {
> +		read_val = readl_relaxed(base + index);
> +		memcpy(buffer + i, &read_val, 4);
> +	}
>   
> +	memcpy(val, buffer + reg % 4, bytes);
> +	kfree(buffer);
>   	return 0;
>   }
>   
>
Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned
Posted by Dmitry Baryshkov 1 year, 2 months ago 
On Mon, Dec 09, 2024 at 09:55:14AM +0000, Srinivas Kandagatla wrote:
> 
> 
> On 26/10/2024 23:42, Dmitry Baryshkov wrote:
> > From: Naman Jain <quic_namajain@quicinc.com>
> > 
> > Add logic for alignment of address for reading in qfprom driver to avoid
> > NOC error issues due to unaligned access. The problem manifests on the
> > SAR2130P platform, but in msm-5.x kernels the fix is applied
> 
> Is this only issue with SAR2130P?

I don't know. I know that it manifests on SAR2130P, but in the vendor
kernels the fix is applied to all the platforms.

> 
> > uncoditionally. Follow this approach and uncoditionally perform aligned
> > reads.
> 
> If there is a need of having proper register alignment this should go as
> part of the nvmem_config->stride and word_size configuration and not in
> reg_read callbacks.

Thanks, I'll explore that option. Indeed, it might be easier to handle.

-- 
With best wishes
Dmitry
Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned
Posted by Akhil P Oommen 1 year, 1 month ago 
On 12/9/2024 4:23 PM, Dmitry Baryshkov wrote:
> On Mon, Dec 09, 2024 at 09:55:14AM +0000, Srinivas Kandagatla wrote:
>>
>>
>> On 26/10/2024 23:42, Dmitry Baryshkov wrote:
>>> From: Naman Jain <quic_namajain@quicinc.com>
>>>
>>> Add logic for alignment of address for reading in qfprom driver to avoid
>>> NOC error issues due to unaligned access. The problem manifests on the
>>> SAR2130P platform, but in msm-5.x kernels the fix is applied
>>
>> Is this only issue with SAR2130P?

This is applicable to all chipsets with sys arch newer than Snapdragon 8
Gen 1.

> 
> I don't know. I know that it manifests on SAR2130P, but in the vendor
> kernels the fix is applied to all the platforms.
> 
>>
>>> uncoditionally. Follow this approach and uncoditionally perform aligned
>>> reads.
>>
>> If there is a need of having proper register alignment this should go as
>> part of the nvmem_config->stride and word_size configuration and not in
>> reg_read callbacks.
> 
> Thanks, I'll explore that option. Indeed, it might be easier to handle.

Dmitry, any update here? I need similar change for X1E GPU speedbin support.

-Akhil

>
Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned
Posted by Dmitry Baryshkov 1 year, 1 month ago 
On Mon, Dec 30, 2024 at 01:13:08PM +0530, Akhil P Oommen wrote:
> On 12/9/2024 4:23 PM, Dmitry Baryshkov wrote:
> > On Mon, Dec 09, 2024 at 09:55:14AM +0000, Srinivas Kandagatla wrote:
> >>
> >>
> >> On 26/10/2024 23:42, Dmitry Baryshkov wrote:
> >>> From: Naman Jain <quic_namajain@quicinc.com>
> >>>
> >>> Add logic for alignment of address for reading in qfprom driver to avoid
> >>> NOC error issues due to unaligned access. The problem manifests on the
> >>> SAR2130P platform, but in msm-5.x kernels the fix is applied
> >>
> >> Is this only issue with SAR2130P?
> 
> This is applicable to all chipsets with sys arch newer than Snapdragon 8
> Gen 1.
> 
> > 
> > I don't know. I know that it manifests on SAR2130P, but in the vendor
> > kernels the fix is applied to all the platforms.
> > 
> >>
> >>> uncoditionally. Follow this approach and uncoditionally perform aligned
> >>> reads.
> >>
> >> If there is a need of having proper register alignment this should go as
> >> part of the nvmem_config->stride and word_size configuration and not in
> >> reg_read callbacks.
> > 
> > Thanks, I'll explore that option. Indeed, it might be easier to handle.
> 
> Dmitry, any update here? I need similar change for X1E GPU speedbin support.

Excuse me for the delay, I've sent v3, reworking the series as
requested:

https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org/

-- 
With best wishes
Dmitry
Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned
Posted by Akhil P Oommen 1 year, 1 month ago 
On 1/4/2025 1:10 PM, Dmitry Baryshkov wrote:
> On Mon, Dec 30, 2024 at 01:13:08PM +0530, Akhil P Oommen wrote:
>> On 12/9/2024 4:23 PM, Dmitry Baryshkov wrote:
>>> On Mon, Dec 09, 2024 at 09:55:14AM +0000, Srinivas Kandagatla wrote:
>>>>
>>>>
>>>> On 26/10/2024 23:42, Dmitry Baryshkov wrote:
>>>>> From: Naman Jain <quic_namajain@quicinc.com>
>>>>>
>>>>> Add logic for alignment of address for reading in qfprom driver to avoid
>>>>> NOC error issues due to unaligned access. The problem manifests on the
>>>>> SAR2130P platform, but in msm-5.x kernels the fix is applied
>>>>
>>>> Is this only issue with SAR2130P?
>>
>> This is applicable to all chipsets with sys arch newer than Snapdragon 8
>> Gen 1.
>>
>>>
>>> I don't know. I know that it manifests on SAR2130P, but in the vendor
>>> kernels the fix is applied to all the platforms.
>>>
>>>>
>>>>> uncoditionally. Follow this approach and uncoditionally perform aligned
>>>>> reads.
>>>>
>>>> If there is a need of having proper register alignment this should go as
>>>> part of the nvmem_config->stride and word_size configuration and not in
>>>> reg_read callbacks.
>>>
>>> Thanks, I'll explore that option. Indeed, it might be easier to handle.
>>
>> Dmitry, any update here? I need similar change for X1E GPU speedbin support.
> 
> Excuse me for the delay, I've sent v3, reworking the series as
> requested:
> 
> https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org/
> 

No issues. Thanks a lot for getting this done.

-Akhil.

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