Similar to regular resizable BAR, VF BAR can also be resized, e.g. by
the system firmware or the PCI subsystem itself.
Add the capability ID and restore it as a part of IOV state.
See PCIe r4.0, sec 9.3.7.4.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
drivers/pci/iov.c | 29 ++++++++++++++++++++++++++++-
include/uapi/linux/pci_regs.h | 1 +
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index aaa33e8dc4c97..6bdc9950b9787 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -7,6 +7,7 @@
* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
*/
+#include <linux/bitfield.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/export.h>
@@ -862,6 +863,30 @@ static void sriov_release(struct pci_dev *dev)
dev->sriov = NULL;
}
+static void sriov_restore_vf_rebar_state(struct pci_dev *dev)
+{
+ unsigned int pos, nbars, i;
+ u32 ctrl;
+
+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VF_REBAR);
+ if (!pos)
+ return;
+
+ pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl);
+ nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl);
+
+ for (i = 0; i < nbars; i++, pos += 8) {
+ int bar_idx, size;
+
+ pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl);
+ bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl);
+ size = pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]);
+ ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
+ ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
+ pci_write_config_dword(dev, pos + PCI_REBAR_CTRL, ctrl);
+ }
+}
+
static void sriov_restore_state(struct pci_dev *dev)
{
int i;
@@ -1021,8 +1046,10 @@ resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno)
*/
void pci_restore_iov_state(struct pci_dev *dev)
{
- if (dev->is_physfn)
+ if (dev->is_physfn) {
+ sriov_restore_vf_rebar_state(dev);
sriov_restore_state(dev);
+ }
}
/**
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 12323b3334a9c..a0cf701c4c3af 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -740,6 +740,7 @@
#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
+#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */
#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
--
2.47.0
Am 25.10.24 um 23:50 schrieb Michał Winiarski: > Similar to regular resizable BAR, VF BAR can also be resized, e.g. by > the system firmware or the PCI subsystem itself. > > Add the capability ID and restore it as a part of IOV state. > > See PCIe r4.0, sec 9.3.7.4. > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> > Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Christian König <christian.koenig@amd.com> > --- > drivers/pci/iov.c | 29 ++++++++++++++++++++++++++++- > include/uapi/linux/pci_regs.h | 1 + > 2 files changed, 29 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c > index aaa33e8dc4c97..6bdc9950b9787 100644 > --- a/drivers/pci/iov.c > +++ b/drivers/pci/iov.c > @@ -7,6 +7,7 @@ > * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com> > */ > > +#include <linux/bitfield.h> > #include <linux/pci.h> > #include <linux/slab.h> > #include <linux/export.h> > @@ -862,6 +863,30 @@ static void sriov_release(struct pci_dev *dev) > dev->sriov = NULL; > } > > +static void sriov_restore_vf_rebar_state(struct pci_dev *dev) > +{ > + unsigned int pos, nbars, i; > + u32 ctrl; > + > + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VF_REBAR); > + if (!pos) > + return; > + > + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); > + nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); > + > + for (i = 0; i < nbars; i++, pos += 8) { > + int bar_idx, size; > + > + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); > + bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); > + size = pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]); > + ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; > + ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); > + pci_write_config_dword(dev, pos + PCI_REBAR_CTRL, ctrl); > + } > +} > + > static void sriov_restore_state(struct pci_dev *dev) > { > int i; > @@ -1021,8 +1046,10 @@ resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno) > */ > void pci_restore_iov_state(struct pci_dev *dev) > { > - if (dev->is_physfn) > + if (dev->is_physfn) { > + sriov_restore_vf_rebar_state(dev); > sriov_restore_state(dev); > + } > } > > /** > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 12323b3334a9c..a0cf701c4c3af 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -740,6 +740,7 @@ > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ > #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ > +#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */ > #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ > #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
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