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[PATCH 2/7] clk: qcom: rpmh: Add support for SM8750 rpmh clocks

Melody Olvera posted 7 patches 1 year, 3 months ago
There is a newer version of this series
[PATCH 2/7] clk: qcom: rpmh: Add support for SM8750 rpmh clocks
Posted by Melody Olvera 1 year, 3 months ago 
From: Taniya Das <quic_tdas@quicinc.com>

Add the RPMH clocks present in SM8750 SoC.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 drivers/clk/qcom/clk-rpmh.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 4acde937114a..245bdfe4827d 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -344,6 +344,7 @@ static const struct clk_ops clk_rpmh_bcm_ops = {
 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1);
 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
+DEFINE_CLK_RPMH_ARC(xo_pad,  "xo.lvl", 0x3, 2);
 DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
 
 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
@@ -368,6 +369,10 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
 DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
 DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
 
+DEFINE_CLK_RPMH_VRM(rf_clk3, _a2, "rfclka3", 2);
+DEFINE_CLK_RPMH_VRM(rf_clk4, _a2, "rfclka4", 2);
+DEFINE_CLK_RPMH_VRM(rf_clk5, _a2, "rfclka5", 2);
+
 DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);
 DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
 DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
@@ -795,6 +800,26 @@ static const struct clk_rpmh_desc clk_rpmh_x1e80100 = {
 	.num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks),
 };
 
+static struct clk_hw *sm8750_rpmh_clocks[] = {
+	[RPMH_CXO_PAD_CLK]      = &clk_rpmh_xo_pad_div2.hw,
+	[RPMH_CXO_PAD_CLK_A]    = &clk_rpmh_xo_pad_div2_ao.hw,
+	[RPMH_LN_BB_CLK1]	= &clk_rpmh_clk6_a2.hw,
+	[RPMH_LN_BB_CLK1_A]	= &clk_rpmh_clk6_a2_ao.hw,
+	[RPMH_LN_BB_CLK3]	= &clk_rpmh_clk8_a2.hw,
+	[RPMH_LN_BB_CLK3_A]	= &clk_rpmh_clk8_a2_ao.hw,
+	[RPMH_RF_CLK1]		= &clk_rpmh_rf_clk1_a.hw,
+	[RPMH_RF_CLK1_A]	= &clk_rpmh_rf_clk1_a_ao.hw,
+	[RPMH_RF_CLK2]		= &clk_rpmh_rf_clk2_a.hw,
+	[RPMH_RF_CLK2_A]	= &clk_rpmh_rf_clk2_a_ao.hw,
+	[RPMH_RF_CLK3]		= &clk_rpmh_rf_clk3_a2.hw,
+	[RPMH_RF_CLK3_A]	= &clk_rpmh_rf_clk3_a2_ao.hw,
+	[RPMH_IPA_CLK]		= &clk_rpmh_ipa.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
+	.clks = sm8750_rpmh_clocks,
+	.num_clks = ARRAY_SIZE(sm8750_rpmh_clocks),
+};
 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
 					 void *data)
 {
@@ -896,6 +921,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
 	{ .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
 	{ .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
 	{ .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650},
+	{ .compatible = "qcom,sm8750-rpmh-clk", .data = &clk_rpmh_sm8750},
 	{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
 	{ .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100},
 	{ }
-- 
2.46.1
Re: [PATCH 2/7] clk: qcom: rpmh: Add support for SM8750 rpmh clocks
Posted by Bjorn Andersson 1 year, 3 months ago 
On Mon, Oct 21, 2024 at 04:03:54PM GMT, Melody Olvera wrote:
> From: Taniya Das <quic_tdas@quicinc.com>
> 
> Add the RPMH clocks present in SM8750 SoC.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
>  drivers/clk/qcom/clk-rpmh.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index 4acde937114a..245bdfe4827d 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -344,6 +344,7 @@ static const struct clk_ops clk_rpmh_bcm_ops = {
>  DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1);
>  DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
>  DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
> +DEFINE_CLK_RPMH_ARC(xo_pad,  "xo.lvl", 0x3, 2);

Please make a note in the commit message documenting why we need two
different xo.lvl resources defined.

If we indeed should have two copies, this list is sorted alphabetically
on the clock name - rather than on the resource. Please keep that (i.e.
move this down one line).

>  DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
>  
>  DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
> @@ -368,6 +369,10 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
>  DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
>  DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
>  
> +DEFINE_CLK_RPMH_VRM(rf_clk3, _a2, "rfclka3", 2);
> +DEFINE_CLK_RPMH_VRM(rf_clk4, _a2, "rfclka4", 2);
> +DEFINE_CLK_RPMH_VRM(rf_clk5, _a2, "rfclka5", 2);
> +
>  DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);
>  DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
>  DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
> @@ -795,6 +800,26 @@ static const struct clk_rpmh_desc clk_rpmh_x1e80100 = {
>  	.num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks),
>  };
>  
> +static struct clk_hw *sm8750_rpmh_clocks[] = {
> +	[RPMH_CXO_PAD_CLK]      = &clk_rpmh_xo_pad_div2.hw,
> +	[RPMH_CXO_PAD_CLK_A]    = &clk_rpmh_xo_pad_div2_ao.hw,
> +	[RPMH_LN_BB_CLK1]	= &clk_rpmh_clk6_a2.hw,
> +	[RPMH_LN_BB_CLK1_A]	= &clk_rpmh_clk6_a2_ao.hw,
> +	[RPMH_LN_BB_CLK3]	= &clk_rpmh_clk8_a2.hw,
> +	[RPMH_LN_BB_CLK3_A]	= &clk_rpmh_clk8_a2_ao.hw,
> +	[RPMH_RF_CLK1]		= &clk_rpmh_rf_clk1_a.hw,
> +	[RPMH_RF_CLK1_A]	= &clk_rpmh_rf_clk1_a_ao.hw,
> +	[RPMH_RF_CLK2]		= &clk_rpmh_rf_clk2_a.hw,
> +	[RPMH_RF_CLK2_A]	= &clk_rpmh_rf_clk2_a_ao.hw,
> +	[RPMH_RF_CLK3]		= &clk_rpmh_rf_clk3_a2.hw,
> +	[RPMH_RF_CLK3_A]	= &clk_rpmh_rf_clk3_a2_ao.hw,
> +	[RPMH_IPA_CLK]		= &clk_rpmh_ipa.hw,
> +};
> +
> +static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
> +	.clks = sm8750_rpmh_clocks,
> +	.num_clks = ARRAY_SIZE(sm8750_rpmh_clocks),
> +};

Please add an empty line here, when you're resubmitting the series.

Thanks,
Bjorn

>  static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
>  					 void *data)
>  {
> @@ -896,6 +921,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
>  	{ .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
>  	{ .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
>  	{ .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650},
> +	{ .compatible = "qcom,sm8750-rpmh-clk", .data = &clk_rpmh_sm8750},
>  	{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
>  	{ .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100},
>  	{ }
> -- 
> 2.46.1
>
Re: [PATCH 2/7] clk: qcom: rpmh: Add support for SM8750 rpmh clocks
Posted by Taniya Das 1 year, 3 months ago 

On 10/23/2024 9:10 AM, Bjorn Andersson wrote:
> On Mon, Oct 21, 2024 at 04:03:54PM GMT, Melody Olvera wrote:
>> From: Taniya Das <quic_tdas@quicinc.com>
>>
>> Add the RPMH clocks present in SM8750 SoC.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>>   drivers/clk/qcom/clk-rpmh.c | 26 ++++++++++++++++++++++++++
>>   1 file changed, 26 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
>> index 4acde937114a..245bdfe4827d 100644
>> --- a/drivers/clk/qcom/clk-rpmh.c
>> +++ b/drivers/clk/qcom/clk-rpmh.c
>> @@ -344,6 +344,7 @@ static const struct clk_ops clk_rpmh_bcm_ops = {
>>   DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1);
>>   DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
>>   DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
>> +DEFINE_CLK_RPMH_ARC(xo_pad,  "xo.lvl", 0x3, 2);
> 
> Please make a note in the commit message documenting why we need two
> different xo.lvl resources defined.
> 
> If we indeed should have two copies, this list is sorted alphabetically
> on the clock name - rather than on the resource. Please keep that (i.e.
> move this down one line).
> 

I will remove the newly added "xo_pad" and reuse the exisiting nodes to 
derive 19.2MHZ.

>>   DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
>>   
>>   DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
>> @@ -368,6 +369,10 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
>>   DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
>>   DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
>>   
>> +DEFINE_CLK_RPMH_VRM(rf_clk3, _a2, "rfclka3", 2);
>> +DEFINE_CLK_RPMH_VRM(rf_clk4, _a2, "rfclka4", 2);
>> +DEFINE_CLK_RPMH_VRM(rf_clk5, _a2, "rfclka5", 2);
>> +
>>   DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);
>>   DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
>>   DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
>> @@ -795,6 +800,26 @@ static const struct clk_rpmh_desc clk_rpmh_x1e80100 = {
>>   	.num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks),
>>   };
>>   
>> +static struct clk_hw *sm8750_rpmh_clocks[] = {
>> +	[RPMH_CXO_PAD_CLK]      = &clk_rpmh_xo_pad_div2.hw,
>> +	[RPMH_CXO_PAD_CLK_A]    = &clk_rpmh_xo_pad_div2_ao.hw,
>> +	[RPMH_LN_BB_CLK1]	= &clk_rpmh_clk6_a2.hw,
>> +	[RPMH_LN_BB_CLK1_A]	= &clk_rpmh_clk6_a2_ao.hw,
>> +	[RPMH_LN_BB_CLK3]	= &clk_rpmh_clk8_a2.hw,
>> +	[RPMH_LN_BB_CLK3_A]	= &clk_rpmh_clk8_a2_ao.hw,
>> +	[RPMH_RF_CLK1]		= &clk_rpmh_rf_clk1_a.hw,
>> +	[RPMH_RF_CLK1_A]	= &clk_rpmh_rf_clk1_a_ao.hw,
>> +	[RPMH_RF_CLK2]		= &clk_rpmh_rf_clk2_a.hw,
>> +	[RPMH_RF_CLK2_A]	= &clk_rpmh_rf_clk2_a_ao.hw,
>> +	[RPMH_RF_CLK3]		= &clk_rpmh_rf_clk3_a2.hw,
>> +	[RPMH_RF_CLK3_A]	= &clk_rpmh_rf_clk3_a2_ao.hw,
>> +	[RPMH_IPA_CLK]		= &clk_rpmh_ipa.hw,
>> +};
>> +
>> +static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
>> +	.clks = sm8750_rpmh_clocks,
>> +	.num_clks = ARRAY_SIZE(sm8750_rpmh_clocks),
>> +};
> 
> Please add an empty line here, when you're resubmitting the series.
> 

Will fix this in the next patch.

> Thanks,
> Bjorn
> 
>>   static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
>>   					 void *data)
>>   {
>> @@ -896,6 +921,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
>>   	{ .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
>>   	{ .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
>>   	{ .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650},
>> +	{ .compatible = "qcom,sm8750-rpmh-clk", .data = &clk_rpmh_sm8750},
>>   	{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
>>   	{ .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100},
>>   	{ }
>> -- 
>> 2.46.1
>>

-- 
Thanks & Regards,
Taniya Das.
Re: [PATCH 2/7] clk: qcom: rpmh: Add support for SM8750 rpmh clocks
Posted by Bryan O'Donoghue 1 year, 3 months ago 
On 22/10/2024 00:03, Melody Olvera wrote:
> +	{ .compatible = "qcom,sm8750-rpmh-clk", .data = &clk_rpmh_sm8750},
>   	{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},

Might be a nice opportunity to alphabetise this list if you do a V2.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Re: [PATCH 2/7] clk: qcom: rpmh: Add support for SM8750 rpmh clocks
Posted by Taniya Das 1 year, 3 months ago 

On 10/22/2024 2:17 PM, Bryan O'Donoghue wrote:
> On 22/10/2024 00:03, Melody Olvera wrote:
>> +    { .compatible = "qcom,sm8750-rpmh-clk", .data = &clk_rpmh_sm8750},
>>       { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
> 
> Might be a nice opportunity to alphabetise this list if you do a V2.
> 
Will fix in the next patch.

> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

-- 
Thanks & Regards,
Taniya Das.

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