Enable ethernet on the Genio 700 EVK board. It has been tested to work
with speeds up to 1000Gbps.
Signed-off-by: Jianguo Zhang <jianguo.zhang@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: Hsuan-Yu Lin <shane.lin@canonical.com>
Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
Signed-off-by: fanyi zhang <fanyi.zhang@mediatek.com>
[Cleaned up to pass dtbs_check, follow DTS style guidelines, and split
between mt8188 and genio700 commits]
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
.../boot/dts/mediatek/mt8390-genio-700-evk.dts | 25 ++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
index 0a6c9871b41e5f913740e68853aea78bc33d02aa..73e34e98726d36785e8b2cef73f532b6bb07c97f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
@@ -24,6 +24,7 @@ / {
aliases {
serial0 = &uart0;
+ ethernet0 = ð
};
chosen {
@@ -845,6 +846,30 @@ pins-wifi-enable {
};
};
+ð {
+ phy-mode ="rgmii-rxid";
+ phy-handle = <ðernet_phy0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <ð_default_pins>;
+ pinctrl-1 = <ð_sleep_pins>;
+ snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>;
+ snps,reset-delays-us = <0 10000 10000>;
+ mediatek,tx-delay-ps = <2030>;
+ mediatek,mac-wol;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ };
+ };
+};
+
&pmic {
interrupt-parent = <&pio>;
interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
--
2.47.0
On Tue, Oct 15, 2024 at 02:15:02PM -0400, Nícolas F. R. A. Prado wrote: > Enable ethernet on the Genio 700 EVK board. It has been tested to work > with speeds up to 1000Gbps. 1000Gbps? NVIDIA needs to watch out. Andrew
Il 15/10/24 20:15, Nícolas F. R. A. Prado ha scritto:
> Enable ethernet on the Genio 700 EVK board. It has been tested to work
> with speeds up to 1000Gbps.
>
> Signed-off-by: Jianguo Zhang <jianguo.zhang@mediatek.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> Signed-off-by: Hsuan-Yu Lin <shane.lin@canonical.com>
> Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
> Signed-off-by: fanyi zhang <fanyi.zhang@mediatek.com>
> [Cleaned up to pass dtbs_check, follow DTS style guidelines, and split
> between mt8188 and genio700 commits]
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
> .../boot/dts/mediatek/mt8390-genio-700-evk.dts | 25 ++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
> index 0a6c9871b41e5f913740e68853aea78bc33d02aa..73e34e98726d36785e8b2cef73f532b6bb07c97f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
> @@ -24,6 +24,7 @@ / {
>
> aliases {
> serial0 = &uart0;
> + ethernet0 = ð
> };
>
> chosen {
> @@ -845,6 +846,30 @@ pins-wifi-enable {
> };
> };
>
> +ð {
> + phy-mode ="rgmii-rxid";
> + phy-handle = <ðernet_phy0>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <ð_default_pins>;
> + pinctrl-1 = <ð_sleep_pins>;
> + snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>;
> + snps,reset-delays-us = <0 10000 10000>;
> + mediatek,tx-delay-ps = <2030>;
> + mediatek,mac-wol;
mediatek,mac-wol;
mediatek,tx-delay-ps = <2030>;
snps,reset-delays-us = <0 10000 10000>;
snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>;
Cheers,
Angelo
> + status = "okay";
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethernet_phy0: ethernet-phy@1 {
> + compatible = "ethernet-phy-id001c.c916";
> + reg = <0x1>;
> + };
> + };
> +};
> +
> &pmic {
> interrupt-parent = <&pio>;
> interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
>
> +ð {
> + phy-mode ="rgmii-rxid";
> + phy-handle = <ðernet_phy0>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <ð_default_pins>;
> + pinctrl-1 = <ð_sleep_pins>;
> + snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>;
> + snps,reset-delays-us = <0 10000 10000>;
> + mediatek,tx-delay-ps = <2030>;
Can you set phy-mode to rgmii-id, and remove the tx-delay-ps property?
Andrew
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