1. Add camera isp7x module device document
2. Add camera interface device document
Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
---
.../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++
.../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++
.../media/mediatek/mediatek,camisp.yaml | 71 ++++++++
.../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++
.../media/mediatek/mediatek,seninf.yaml | 88 +++++++++
5 files changed, 582 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
new file mode 100644
index 000000000000..c709e4bf0a18
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The cam-raw unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
+
+properties:
+ compatible:
+ const: mediatek,cam-raw
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ reg:
+ items:
+ minItems: 2
+ maxItems: 4
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
+
+ mediatek,cam-id:
+ description:
+ Describes the index of MediaTek cam-raw unit for ISP
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ mediatek,larbs:
+ description:
+ Describes MediaTek bus infrastructure unit for ISP system.
+ List of phandle to the local arbiters in the current SoCs.
+ Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+ interrupts:
+ minItems: 1
+
+ dma-ranges:
+ description:
+ Describes the address information of IOMMU mapping to memory.
+ Defines six fields for the MediaTek IOMMU extended iova, pa, and size.
+ minItems: 1
+
+ power-domains:
+ minItems: 1
+
+ clocks:
+ minItems: 4
+ maxItems: 16
+
+ clock-names:
+ minItems: 4
+ maxItems: 16
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ iommus:
+ description:
+ Points to the respective IOMMU block with master port as argument, see
+ Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ Ports are according to the HW.
+ minItems: 1
+ maxItems: 32
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - power-domains
+ - clocks
+ - clock-names
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+ #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cam_raw_a@16030000 {
+ compatible = "mediatek,cam-raw";
+ reg = <0 0x16030000 0 0x8000>,
+ <0 0x16038000 0 0x8000>;
+ reg-names = "base", "inner_base";
+ mediatek,cam-id = <0>;
+ mediatek,larbs = <&larb16a>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
+ clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM>,
+ <&camsys CLK_CAM_MAIN_CAMTG>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>,
+ <&camsys_rawa CLK_CAM_RAWA_CAM>,
+ <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
+ <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_CAMTG>,
+ <&topckgen CLK_TOP_CAMTM>;
+ clock-names = "camsys_cam2mm0_cgpdn",
+ "camsys_cam2mm1_cgpdn",
+ "camsys_cam2sys_cgpdn",
+ "camsys_cam_cgpdn",
+ "camsys_camtg_cgpdn",
+ "camsys_rawa_larbx_cgpdn",
+ "camsys_rawa_cam_cgpdn",
+ "camsys_rawa_camtg_cgpdn",
+ "topckgen_top_cam",
+ "topckgen_top_camtg",
+ "topckgen_top_camtm";
+ assigned-clocks = <&topckgen CLK_TOP_CAM>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
+ iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
+ <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
+ <&vpp_iommu M4U_PORT_L16A_CQI_R2>,
+ <&vpp_iommu M4U_PORT_L16A_BPCI_R1>,
+ <&vpp_iommu M4U_PORT_L16A_LSCI_R1>,
+ <&vpp_iommu M4U_PORT_L16A_RAWI_R2>,
+ <&vpp_iommu M4U_PORT_L16A_RAWI_R3>,
+ <&vpp_iommu M4U_PORT_L16A_UFDI_R2>,
+ <&vpp_iommu M4U_PORT_L16A_UFDI_R3>,
+ <&vpp_iommu M4U_PORT_L16A_RAWI_R4>,
+ <&vpp_iommu M4U_PORT_L16A_RAWI_R5>,
+ <&vpp_iommu M4U_PORT_L16A_AAI_R1>,
+ <&vpp_iommu M4U_PORT_L16A_UFDI_R5>,
+ <&vpp_iommu M4U_PORT_L16A_FHO_R1>,
+ <&vpp_iommu M4U_PORT_L16A_AAO_R1>,
+ <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>,
+ <&vpp_iommu M4U_PORT_L16A_FLKO_R1>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
new file mode 100644
index 000000000000..30dfd5e5ecb1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-yuv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The cam-yuv unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek cam-yuv is the camera YUV processing unit in MediaTek SoC.
+
+properties:
+ compatible:
+ const: mediatek,cam-yuv
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ reg:
+ items:
+ minItems: 2
+ maxItems: 4
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
+
+ mediatek,cam-id:
+ description:
+ Describes the index of MediaTek cam-yuv unit for ISP
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ mediatek,larbs:
+ description:
+ Describes MediaTek bus infrastructure unit for ISP system.
+ List of phandle to the local arbiters in the current SoCs.
+ Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+ interrupts:
+ minItems: 1
+
+ dma-ranges:
+ description:
+ Describes the address information of IOMMU mapping to memory.
+ Defines six fields for the MediaTek IOMMU extended iova, pa, and size.
+ minItems: 1
+
+ power-domains:
+ minItems: 1
+
+ clocks:
+ minItems: 4
+ maxItems: 16
+
+ clock-names:
+ minItems: 4
+ maxItems: 16
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ iommus:
+ description:
+ Points to the respective IOMMU block with master port as argument, see
+ Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ Ports are according to the HW.
+ minItems: 1
+ maxItems: 32
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - power-domains
+ - clocks
+ - clock-names
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+ #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cam_yuv_b@16090000 {
+ compatible = "mediatek,cam-yuv";
+ reg = <0 0x16090000 0 0x8000>;
+ reg-names = "base";
+ mediatek,cam-id = <1>;
+ mediatek,larbs = <&larb17b>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBB>;
+ clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
+ <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
+ <&camsys_yuvb CLK_CAM_YUVB_CAM>,
+ <&camsys_yuvb CLK_CAM_YUVB_CAMTG>;
+ clock-names = "camsys_cam2mm0_cgpdn",
+ "camsys_cam2mm1_cgpdn",
+ "camsys_cam2sys_cgpdn",
+ "camsys_yuvb_larbx_cgpdn",
+ "camsys_yuvb_cam_cgpdn",
+ "camsys_yuvb_camtg_cgpdn";
+ assigned-clocks = <&topckgen CLK_TOP_CAM>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
+ iommus = <&vdo_iommu M4U_PORT_L17B_YUVO_R1>,
+ <&vdo_iommu M4U_PORT_L17B_YUVO_R3>,
+ <&vdo_iommu M4U_PORT_L17B_YUVCO_R1>,
+ <&vdo_iommu M4U_PORT_L17B_YUVO_R2>,
+ <&vdo_iommu M4U_PORT_L17B_RZH1N2TO_R1>,
+ <&vdo_iommu M4U_PORT_L17B_DRZS4NO_R1>,
+ <&vdo_iommu M4U_PORT_L17B_TNCSO_R1>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
new file mode 100644
index 000000000000..ce378ddbd5bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,camisp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The camisp unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek camisp is the ISP auxiliary unit for camera system in MediaTek SoC.
+
+properties:
+ compatible:
+ const: mediatek,camisp
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ reg:
+ items:
+ minItems: 2
+ maxItems: 4
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ mediatek,scp:
+ description: MediaTek co-process unit for ISP system
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camisp: camisp@16000000 {
+ compatible = "mediatek,camisp";
+ reg = <0 0x16000000 0 0x1000>;
+ reg-names = "base";
+ mediatek,scp = <&scp_dual>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_CAM_MAIN>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
new file mode 100644
index 000000000000..bc509976a79e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,seninf-core.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The seninf-core top unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek seninf-core is the ISP sensor interface unit in MediaTek SoC.
+ The sensor interface serves as the MIPI-CSI2 top RX controller.
+
+properties:
+ compatible:
+ const: mediatek,seninf-core
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ reg:
+ items:
+ minItems: 2
+ maxItems: 4
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 2
+ maxItems: 2
+
+ mtk_csi_phy_ver:
+ description:
+ Describes MediaTek camera Rx controller version
+ $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ power-domains:
+ minItems: 1
+ maxItems: 4
+
+ clocks:
+ minItems: 3
+ maxItems: 8
+
+ clock-names:
+ minItems: 3
+ maxItems: 8
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - power-domains
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ seninf_top: seninf_top@16010000 {
+ compatible = "mediatek,seninf-core";
+ reg = <0 0x16010000 0 0x8000>,
+ <0 0x11ed0000 0 0xc000>;
+ reg-names = "base", "ana-rx";
+ mtk_csi_phy_ver = "mtk_csi_phy_2_0";
+ interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_CSIRX_TOP>,
+ <&spm MT8188_POWER_DOMAIN_CAM_VCORE>,
+ <&spm MT8188_POWER_DOMAIN_CAM_MAIN>;
+ clocks = <&camsys CLK_CAM_MAIN_SENINF>,
+ <&topckgen CLK_TOP_SENINF>,
+ <&topckgen CLK_TOP_SENINF1>,
+ <&topckgen CLK_TOP_CAMTM>;
+ clock-names = "clk_cam_seninf",
+ "clk_top_seninf",
+ "clk_top_seninf1",
+ "clk_top_camtm";
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
new file mode 100644
index 000000000000..37d94138c558
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek/mediatek,seninf.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The seninf unit of MediaTek ISP system
+
+maintainers:
+ - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
+ - Shun-yi Wang <shun-yi.wang@mediatek.com>
+ - Teddy Chen <teddy.chen@mediatek.com>
+
+description:
+ MediaTek seninf is the MIPI-CSI2 port for seninf-core in MediaTek SoC.
+ These ports provide the optional capability to define endpoints and set RX
+ controller for camera sensors.
+
+properties:
+ compatible:
+ const: mediatek,seninf
+
+ csi-port:
+ description: MediaTek CSI Rx port name
+ $ref: /schemas/types.yaml#/definitions/string
+
+ port:
+ description:
+ MediaTek sensor interface endpoints for one sensor bus.
+ $ref: /schemas/graph.yaml#/$defs/port-base
+
+ properties:
+ "#address-cells":
+ const: 1
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^endpoint(@[0-9]+)?$":
+ description:
+ CSI port for one sensor endpoint configuration.
+ Consider one sensor bus can support differet links for MIPI PHY.
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+ properties:
+ data-lanes:
+ items:
+ enum: [1, 2, 3, 4]
+ maxItems: 4
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - csi-port
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ seninf_top {
+ seninf_csi_port_0: seninf_csi_port_0 {
+ compatible = "mediatek,seninf";
+ csi-port = "0A";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ seninf_csi_port_0_in_1: endpoint {
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <1440000000 624000000>;
+ remote-endpoint = <&sensor0_out_1>;
+ };
+
+ seninf_csi_port_0_in_2: endpoint@2 {
+ reg = <2>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <336000000 207000000>;
+ remote-endpoint = <&sensor0_out_2>;
+ };
+ };
+ };
+ };
+
+...
--
2.18.0Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPnhKvzWQ$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The cam-raw unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,cam-raw
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + reg:
> + items:
> + minItems: 2
> + maxItems: 4
> + minItems: 1
> + maxItems: 2
> +
> + reg-names:
> + minItems: 1
> + maxItems: 2
> +
> + mediatek,cam-id:
> + description:
> + Describes the index of MediaTek cam-raw unit for ISP
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + mediatek,larbs:
> + description:
> + Describes MediaTek bus infrastructure unit for ISP system.
> + List of phandle to the local arbiters in the current SoCs.
> + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + minItems: 1
> + maxItems: 32
> +
> + interrupts:
> + minItems: 1
> +
> + dma-ranges:
> + description:
> + Describes the address information of IOMMU mapping to memory.
> + Defines six fields for the MediaTek IOMMU extended iova, pa, and size.
> + minItems: 1
> +
> + power-domains:
> + minItems: 1
> +
> + clocks:
> + minItems: 4
> + maxItems: 16
> +
> + clock-names:
> + minItems: 4
> + maxItems: 16
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
> +
> + iommus:
> + description:
> + Points to the respective IOMMU block with master port as argument, see
> + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> + Ports are according to the HW.
> + minItems: 1
> + maxItems: 32
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - power-domains
> + - clocks
> + - clock-names
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mediatek,mt8188-power.h>
> + #include <dt-bindings/clock/mediatek,mt8188-clk.h>
> + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cam_raw_a@16030000 {
> + compatible = "mediatek,cam-raw";
> + reg = <0 0x16030000 0 0x8000>,
> + <0 0x16038000 0 0x8000>;
It could be
reg = <0 0x16030000 0 0x10000>;
Why do you break it into two part?
> + reg-names = "base", "inner_base";
> + mediatek,cam-id = <0>;
> + mediatek,larbs = <&larb16a>;
larb information is inside iommu device, so it's not necessary to have a larb property here.
Regards,
CK
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
> + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM>,
> + <&camsys CLK_CAM_MAIN_CAMTG>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>,
> + <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
> + <&topckgen CLK_TOP_CAM>,
> + <&topckgen CLK_TOP_CAMTG>,
> + <&topckgen CLK_TOP_CAMTM>;
> + clock-names = "camsys_cam2mm0_cgpdn",
> + "camsys_cam2mm1_cgpdn",
> + "camsys_cam2sys_cgpdn",
> + "camsys_cam_cgpdn",
> + "camsys_camtg_cgpdn",
> + "camsys_rawa_larbx_cgpdn",
> + "camsys_rawa_cam_cgpdn",
> + "camsys_rawa_camtg_cgpdn",
> + "topckgen_top_cam",
> + "topckgen_top_camtg",
> + "topckgen_top_camtm";
> + assigned-clocks = <&topckgen CLK_TOP_CAM>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
> + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_BPCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_LSCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R4>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_AAI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_FHO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_AAO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_FLKO_R1>;
> + };
> + };
> +
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +...
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> new file mode 100644
> index 000000000000..ce378ddbd5bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,camisp.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPg8zy568$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The camisp unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek camisp is the ISP auxiliary unit for camera system in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,camisp
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + reg:
> + items:
> + minItems: 2
> + maxItems: 4
> + minItems: 1
> + maxItems: 2
> +
> + reg-names:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + mediatek,scp:
> + description: MediaTek co-process unit for ISP system
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/power/mediatek,mt8188-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camisp: camisp@16000000 {
In mt8188.dtsi [1], there is already a clock controller at address 16000000.
It should not have two device at the same address.
It should have one device which has multiple function.
mmsys controller [2] is a syscon (system controller) device which has multiple function.
It has a main driver (mmsys driver) [3] and two sub driver: clock driver [4] and display driver [5].
The main driver would probe the sub drivers.
Refer to mmsys device to refine the device at address 16000000.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8188.dtsi?h=v6.12-rc7#n1847
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml?h=v6.12-rc7
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=v6.12-rc7
[4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8188-vdo0.c?h=v6.12-rc7
[5] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_drv.c?h=v6.12-rc7
Regards,
CK
> + compatible = "mediatek,camisp";
> + reg = <0 0x16000000 0 0x1000>;
> + reg-names = "base";
> + mediatek,scp = <&scp_dual>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_MAIN>;
> + };
> + };
> +
On 09/10/2024 13:15, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
> .../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++
> .../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++
> .../media/mediatek/mediatek,camisp.yaml | 71 ++++++++
> .../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++
> .../media/mediatek/mediatek,seninf.yaml | 88 +++++++++
> 5 files changed, 582 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> new file mode 100644
> index 000000000000..c709e4bf0a18
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
Drop blank line
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: The cam-raw unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,cam-raw
SoC specific compatible instead. I see Rob gave you review, so few more
points.
...
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
Drop assigned-clock*
> +
> + iommus:
> + description:
> + Points to the respective IOMMU block with master port as argument, see
> + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> + Ports are according to the HW.
> + minItems: 1
> + maxItems: 32
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - power-domains
> + - clocks
> + - clock-names
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mediatek,mt8188-power.h>
> + #include <dt-bindings/clock/mediatek,mt8188-clk.h>
> + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cam_raw_a@16030000 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
e.g. isp
Also, underscores are not allowed in node names. Please do not send to
us your downstream code. Read DTS coding style and write code maching
upstream style.
> + compatible = "mediatek,cam-raw";
> + reg = <0 0x16030000 0 0x8000>,
> + <0 0x16038000 0 0x8000>;
> + reg-names = "base", "inner_base";
> + mediatek,cam-id = <0>;
> + mediatek,larbs = <&larb16a>;
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
> + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM>,
> + <&camsys CLK_CAM_MAIN_CAMTG>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>,
> + <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
> + <&topckgen CLK_TOP_CAM>,
> + <&topckgen CLK_TOP_CAMTG>,
> + <&topckgen CLK_TOP_CAMTM>;
Messed alignment.
> + clock-names = "camsys_cam2mm0_cgpdn",
> + "camsys_cam2mm1_cgpdn",
> + "camsys_cam2sys_cgpdn",
> + "camsys_cam_cgpdn",
> + "camsys_camtg_cgpdn",
> + "camsys_rawa_larbx_cgpdn",
> + "camsys_rawa_cam_cgpdn",
> + "camsys_rawa_camtg_cgpdn",
> + "topckgen_top_cam",
> + "topckgen_top_camtg",
> + "topckgen_top_camtm";
Also misaligned.
> + assigned-clocks = <&topckgen CLK_TOP_CAM>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
> + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
Also misaligned.
All comments apply to other files as well.
Best regards,
Krzysztof
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
> new file mode 100644
> index 000000000000..37d94138c558
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,seninf.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPVkLta9M$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$
> +
> +title: The seninf unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek seninf is the MIPI-CSI2 port for seninf-core in MediaTek SoC.
> + These ports provide the optional capability to define endpoints and set RX
> + controller for camera sensors.
> +
> +properties:
> + compatible:
> + const: mediatek,seninf
> +
> + csi-port:
> + description: MediaTek CSI Rx port name
> + $ref: /schemas/types.yaml#/definitions/string
> +
> + port:
> + description:
> + MediaTek sensor interface endpoints for one sensor bus.
> + $ref: /schemas/graph.yaml#/$defs/port-base
> +
> + properties:
> + "#address-cells":
> + const: 1
> + "#size-cells":
> + const: 0
> +
> + patternProperties:
> + "^endpoint(@[0-9]+)?$":
> + description:
> + CSI port for one sensor endpoint configuration.
> + Consider one sensor bus can support differet links for MIPI PHY.
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> + properties:
> + data-lanes:
> + items:
> + enum: [1, 2, 3, 4]
> + maxItems: 4
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - csi-port
> + - port
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + seninf_top {
> + seninf_csi_port_0: seninf_csi_port_0 {
> + compatible = "mediatek,seninf";
> + csi-port = "0A";
This device has no reg property, so it's a virtual device not a real device.
binding document is used to describe a real hardware device, so drop this binding document.
There is another seninf device [1] which is upstreaming.
Even though it's not upstreamed yet, it have been reviewed.
You may take it as a reference.
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=874617
Regards,
CK
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + seninf_csi_port_0_in_1: endpoint {
> + data-lanes = <1 2>;
> + link-frequencies = /bits/ 64 <1440000000 624000000>;
> + remote-endpoint = <&sensor0_out_1>;
> + };
> +
> + seninf_csi_port_0_in_2: endpoint@2 {
> + reg = <2>;
> + data-lanes = <1 2>;
> + link-frequencies = /bits/ 64 <336000000 207000000>;
> + remote-endpoint = <&sensor0_out_2>;
> + };
> + };
> + };
> + };
> +
> +...
Hi, Shu-shiang: On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote: > 1. Add camera isp7x module device document > 2. Add camera interface device document > > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com> > --- > .../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++ > .../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++ > .../media/mediatek/mediatek,camisp.yaml | 71 ++++++++ > .../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++ > .../media/mediatek/mediatek,seninf.yaml | 88 +++++++++ Break each binding document to an independent patch and this would make review process easier. For example, there are five patches for each of cam-raw, cam-yuv, camisp, seninf-core, seninf. When I feel good about cam-raw, cam-yuv, camisp, I would give reviewed-by tag on these three patches. After you send new version, I could focus on reviewing seninf-core and seninf. If these are combined into one patch, even I feel good about cam-raw, cam-yuv, camisp, I can not give reviewed-by tag on this patch. After you send new version, I need to review the whole patch again. This would slow down the review process. > 5 files changed, 582 insertions(+) > [snip] > +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml > @@ -0,0 +1,169 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2024 MediaTek Inc. > + > +%YAML 1.2 > +--- > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPnhKvzWQ$ > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$ > + > +title: The cam-raw unit of MediaTek ISP system > + > +maintainers: > + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com> > + - Shun-yi Wang <shun-yi.wang@mediatek.com> > + - Teddy Chen <teddy.chen@mediatek.com> > + > +description: > + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC. > + > +properties: > + compatible: > + const: mediatek,cam-raw mediatek,mt8188-cam-raw > + > + "#address-cells": > + const: 2 > + > [snip] > diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml > new file mode 100644 > index 000000000000..30dfd5e5ecb1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml > @@ -0,0 +1,148 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2024 MediaTek Inc. > + > +%YAML 1.2 > +--- > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,cam-yuv.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPyS5asjc$ > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$ > + > +title: The cam-yuv unit of MediaTek ISP system > + > +maintainers: > + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com> > + - Shun-yi Wang <shun-yi.wang@mediatek.com> > + - Teddy Chen <teddy.chen@mediatek.com> > + > +description: > + MediaTek cam-yuv is the camera YUV processing unit in MediaTek SoC. > + > +properties: > + compatible: > + const: mediatek,cam-yuv mediatek,mt8188-cam-yuv > + > + "#address-cells": > + const: 2 > + > [snip] > diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml > new file mode 100644 > index 000000000000..ce378ddbd5bd > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2024 MediaTek Inc. > + > +%YAML 1.2 > +--- > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,camisp.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPg8zy568$ > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$ > + > +title: The camisp unit of MediaTek ISP system > + > +maintainers: > + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com> > + - Shun-yi Wang <shun-yi.wang@mediatek.com> > + - Teddy Chen <teddy.chen@mediatek.com> > + > +description: > + MediaTek camisp is the ISP auxiliary unit for camera system in MediaTek SoC. > + > +properties: > + compatible: > + const: mediatek,camisp mediatek,mt8188-camisp > + > + "#address-cells": > + const: 2 > + > [snip] > diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml > new file mode 100644 > index 000000000000..bc509976a79e > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml > @@ -0,0 +1,106 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2024 MediaTek Inc. > + > +%YAML 1.2 > +--- > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,seninf-core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPyn0dkZA$ > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$ > + > +title: The seninf-core top unit of MediaTek ISP system > + > +maintainers: > + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com> > + - Shun-yi Wang <shun-yi.wang@mediatek.com> > + - Teddy Chen <teddy.chen@mediatek.com> > + > +description: > + MediaTek seninf-core is the ISP sensor interface unit in MediaTek SoC. > + The sensor interface serves as the MIPI-CSI2 top RX controller. > + > +properties: > + compatible: > + const: mediatek,seninf-core mediatek,mt8188-seninf-core > + > + "#address-cells": > + const: 2 > + > [snip] > diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml > new file mode 100644 > index 000000000000..37d94138c558 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml > @@ -0,0 +1,88 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2024 MediaTek Inc. > + > +%YAML 1.2 > +--- > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,seninf.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPVkLta9M$ > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$ > + > +title: The seninf unit of MediaTek ISP system > + > +maintainers: > + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com> > + - Shun-yi Wang <shun-yi.wang@mediatek.com> > + - Teddy Chen <teddy.chen@mediatek.com> > + > +description: > + MediaTek seninf is the MIPI-CSI2 port for seninf-core in MediaTek SoC. > + These ports provide the optional capability to define endpoints and set RX > + controller for camera sensors. > + > +properties: > + compatible: > + const: mediatek,seninf mediatek,mt8188-seninf Regards, CK > + > + csi-port: > + description: MediaTek CSI Rx port name > + $ref: /schemas/types.yaml#/definitions/string > + >
On Wed, Oct 09, 2024 at 07:15:42PM +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
> .../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++
> .../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++
> .../media/mediatek/mediatek,camisp.yaml | 71 ++++++++
> .../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++
> .../media/mediatek/mediatek,seninf.yaml | 88 +++++++++
> 5 files changed, 582 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> new file mode 100644
> index 000000000000..c709e4bf0a18
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: The cam-raw unit of MediaTek ISP system
> +
> +maintainers:
> + - Shu-hsiang Yang <shu-hsiang.yang@mediatek.com>
> + - Shun-yi Wang <shun-yi.wang@mediatek.com>
> + - Teddy Chen <teddy.chen@mediatek.com>
> +
> +description:
> + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
> +
> +properties:
> + compatible:
> + const: mediatek,cam-raw
Compatibles should be SoC specific.
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
Don't need these. You don't have any child nodes with addresses.
> +
> + reg:
> + items:
> + minItems: 2
> + maxItems: 4
Drop items.
> + minItems: 1
> + maxItems: 2
You have to specify what each region is.
Why does it vary? A h/w block either has register region or it doesn't.
> +
> + reg-names:
> + minItems: 1
> + maxItems: 2
You must define the names.
> +
> + mediatek,cam-id:
> + description:
> + Describes the index of MediaTek cam-raw unit for ISP
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
No, we don't put module indices in DT.
> +
> + mediatek,larbs:
> + description:
> + Describes MediaTek bus infrastructure unit for ISP system.
> + List of phandle to the local arbiters in the current SoCs.
> + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + minItems: 1
> + maxItems: 32
> +
> + interrupts:
> + minItems: 1
> +
> + dma-ranges:
> + description:
> + Describes the address information of IOMMU mapping to memory.
> + Defines six fields for the MediaTek IOMMU extended iova, pa, and size.
> + minItems: 1
> +
> + power-domains:
> + minItems: 1
> +
> + clocks:
> + minItems: 4
> + maxItems: 16
You have to define what the clocks are.
> +
> + clock-names:
> + minItems: 4
> + maxItems: 16
> +
> + assigned-clocks:
> + maxItems: 1
> +
> + assigned-clock-parents:
> + maxItems: 1
Drop. You don't need to document assigned-clocks.
> +
> + iommus:
> + description:
> + Points to the respective IOMMU block with master port as argument, see
> + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> + Ports are according to the HW.
> + minItems: 1
> + maxItems: 32
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - power-domains
> + - clocks
> + - clock-names
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mediatek,mt8188-power.h>
> + #include <dt-bindings/clock/mediatek,mt8188-clk.h>
> + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cam_raw_a@16030000 {
> + compatible = "mediatek,cam-raw";
> + reg = <0 0x16030000 0 0x8000>,
> + <0 0x16038000 0 0x8000>;
> + reg-names = "base", "inner_base";
> + mediatek,cam-id = <0>;
> + mediatek,larbs = <&larb16a>;
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
> + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM>,
> + <&camsys CLK_CAM_MAIN_CAMTG>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>,
> + <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
> + <&topckgen CLK_TOP_CAM>,
> + <&topckgen CLK_TOP_CAMTG>,
> + <&topckgen CLK_TOP_CAMTM>;
> + clock-names = "camsys_cam2mm0_cgpdn",
> + "camsys_cam2mm1_cgpdn",
> + "camsys_cam2sys_cgpdn",
> + "camsys_cam_cgpdn",
> + "camsys_camtg_cgpdn",
> + "camsys_rawa_larbx_cgpdn",
> + "camsys_rawa_cam_cgpdn",
> + "camsys_rawa_camtg_cgpdn",
> + "topckgen_top_cam",
> + "topckgen_top_camtg",
> + "topckgen_top_camtm";
> + assigned-clocks = <&topckgen CLK_TOP_CAM>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
> + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_BPCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_LSCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R4>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_AAI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_FHO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_AAO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_FLKO_R1>;
> + };
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
> new file mode 100644
> index 000000000000..30dfd5e5ecb1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml
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