CXL port error handling will be updated in future and will use
logic to determine if an error requires CXL or PCIe processing.
Internal errors are one indicator to identify an error is a CXL
protocol error.

is_internal_error() is currently limited by CONFIG_PCIEAER_CXL
kernel config.

Update the is_internal_error() function's declaration such that it is
always available regardless if CONFIG_PCIEAER_CXL kernel config
is enabled or disabled.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
 drivers/pci/pcie/aer.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index a9792b9576b4..1e72829a249f 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -941,8 +941,15 @@ static bool find_source_device(struct pci_dev *parent,
 	return true;
 }
 
-#ifdef CONFIG_PCIEAER_CXL
+static bool is_internal_error(struct aer_err_info *info)
+{
+	if (info->severity == AER_CORRECTABLE)
+		return info->status & PCI_ERR_COR_INTERNAL;
 
+	return info->status & PCI_ERR_UNC_INTN;
+}
+
+#ifdef CONFIG_PCIEAER_CXL
 /**
  * pci_aer_unmask_internal_errors - unmask internal errors
  * @dev: pointer to the pcie_dev data structure
@@ -994,14 +1001,6 @@ static bool cxl_error_is_native(struct pci_dev *dev)
 	return (pcie_ports_native || host->native_aer);
 }
 
-static bool is_internal_error(struct aer_err_info *info)
-{
-	if (info->severity == AER_CORRECTABLE)
-		return info->status & PCI_ERR_COR_INTERNAL;
-
-	return info->status & PCI_ERR_UNC_INTN;
-}
-
 static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data)
 {
 	struct aer_err_info *info = (struct aer_err_info *)data;
-- 
2.34.1

Terry Bowman wrote:
> CXL port error handling will be updated in future and will use
> logic to determine if an error requires CXL or PCIe processing.
> Internal errors are one indicator to identify an error is a CXL
> protocol error.

I expect it would better to fold this into the patch that makes use of
the is_internal_error() outside of the CONFIG_PCIEAER_CXL case.

With this patch in isolation it is not clear that a kernel that sets
CONFIG_PCIEAER_CXL=n should distinguish PCIe internal errors from CXL
errors.

The real problem seems to be that CONFIG_PCIEAER_CXL depends on CXL_PCI.
I.e. is_internal_error() only matters for the CXL case, and the CXL
handling is moving more into the core and dropping its CXL_PCI
dependency.

Hi Dan,

On 10/21/24 21:17, Dan Williams wrote:
> Terry Bowman wrote:
>> CXL port error handling will be updated in future and will use
>> logic to determine if an error requires CXL or PCIe processing.
>> Internal errors are one indicator to identify an error is a CXL
>> protocol error.
> 
> I expect it would better to fold this into the patch that makes use of
> the is_internal_error() outside of the CONFIG_PCIEAER_CXL case.
> 
> With this patch in isolation it is not clear that a kernel that sets
> CONFIG_PCIEAER_CXL=n should distinguish PCIe internal errors from CXL
> errors.
> 
> The real problem seems to be that CONFIG_PCIEAER_CXL depends on CXL_PCI.
> I.e. is_internal_error() only matters for the CXL case, and the CXL
> handling is moving more into the core and dropping its CXL_PCI
> dependency.

I will merge the patch as you described.

Regards,
Terry

On Tue, 8 Oct 2024 17:16:44 -0500
Terry Bowman <terry.bowman@amd.com> wrote:

> CXL port error handling will be updated in future and will use
> logic to determine if an error requires CXL or PCIe processing.
> Internal errors are one indicator to identify an error is a CXL
> protocol error.
> 
> is_internal_error() is currently limited by CONFIG_PCIEAER_CXL
> kernel config.
> 
> Update the is_internal_error() function's declaration such that it is
> always available regardless if CONFIG_PCIEAER_CXL kernel config
> is enabled or disabled.
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Given this has nothing specifically to do with CXL, this seems
sensible to me.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>