Convert the bindings to yaml format.
Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
---
.../devicetree/bindings/mtd/davinci-nand.txt | 94 -----------------
.../devicetree/bindings/mtd/ti,davinci-nand.yaml | 115 +++++++++++++++++++++
2 files changed, 115 insertions(+), 94 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt b/Documentation/devicetree/bindings/mtd/davinci-nand.txt
deleted file mode 100644
index eb8e2ff4dbd2901b3c396f2e66c1f590a32dcf67..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-Device tree bindings for Texas instruments Davinci/Keystone NAND controller
-
-This file provides information, what the device node for the davinci/keystone
-NAND interface contains.
-
-Documentation:
-Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
-Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
-
-Required properties:
-
-- compatible: "ti,davinci-nand"
- "ti,keystone-nand"
-
-- reg: Contains 2 offset/length values:
- - offset and length for the access window.
- - offset and length for accessing the AEMIF
- control registers.
-
-- ti,davinci-chipselect: number of chipselect. Indicates on the
- davinci_nand driver which chipselect is used
- for accessing the nand.
- Can be in the range [0-3].
-
-Recommended properties :
-
-- ti,davinci-mask-ale: mask for ALE. Needed for executing address
- phase. These offset will be added to the base
- address for the chip select space the NAND Flash
- device is connected to.
- If not set equal to 0x08.
-
-- ti,davinci-mask-cle: mask for CLE. Needed for executing command
- phase. These offset will be added to the base
- address for the chip select space the NAND Flash
- device is connected to.
- If not set equal to 0x10.
-
-- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
- addresses for given chipselect.
-
-- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
- valid values for davinci driver:
- - "none"
- - "soft"
- - "hw"
-
-- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
-
-- nand-bus-width: buswidth 8 or 16. If not present 8.
-
-- nand-on-flash-bbt: use flash based bad block table support. OOB
- identifier is saved in OOB area. If not present
- false.
-
-Deprecated properties:
-
-- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
- valid values for davinci driver:
- - "none"
- - "soft"
- - "hw"
-
-- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
-
-- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
- identifier is saved in OOB area. If not present
- false.
-
-Nand device bindings may contain additional sub-nodes describing partitions of
-the address space. See mtd.yaml for more detail. The NAND Flash timing
-values must be programmed in the chip select’s node of AEMIF
-memory-controller (see Documentation/devicetree/bindings/memory-controllers/
-davinci-aemif.txt).
-
-Example(da850 EVM ):
-
-nand_cs3@62000000 {
- compatible = "ti,davinci-nand";
- reg = <0x62000000 0x807ff
- 0x68000000 0x8000>;
- ti,davinci-chipselect = <1>;
- ti,davinci-mask-ale = <0>;
- ti,davinci-mask-cle = <0>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x7e80000>;
- };
-};
diff --git a/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..1263616593532e8483d556b4242b004a16620ddf
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI DaVinci NAND controller
+
+maintainers:
+ - Marcus Folkesson <marcus.folkesson@gmail.com>
+
+allOf:
+ - $ref: nand-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,davinci-nand
+ - ti,keystone-nand
+
+ reg:
+ maxItems: 1
+
+ partitions:
+ $ref: /schemas/mtd/partitions/partitions.yaml
+
+ ti,davinci-chipselect:
+ description:
+ Number of chipselect. Indicate on the davinci_nand driver which
+ chipselect is used for accessing the nand.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+
+ ti,davinci-mask-ale:
+ description:
+ Mask for ALE. Needed for executing address phase. These offset will be
+ added to the base address for the chip select space the NAND Flash
+ device is connected to.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x08
+
+ ti,davinci-mask-cle:
+ description:
+ Mask for CLE. Needed for executing command phase. These offset will be
+ added to the base address for the chip select space the NAND Flash device
+ is connected to.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x10
+
+ ti,davinci-mask-chipsel:
+ description:
+ Mask for chipselect address. Needed to mask addresses for given
+ chipselect.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ ti,davinci-ecc-bits:
+ description: Used ECC bits.
+ enum: [1, 4]
+
+ ti,davinci-ecc-mode:
+ description: Operation mode of the NAND ECC mode.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [none, soft, hw, on-die]
+ deprecated: true
+
+ ti,davinci-nand-buswidth:
+ description: Bus width to the NAND chip
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [8, 16]
+ default: 8
+ deprecated: true
+
+ ti,davinci-nand-use-bbt:
+ type: boolean
+ description:
+ Use flash based bad block table support. OOB identifier is saved in OOB
+ area.
+ deprecated: true
+
+required:
+ - compatible
+ - reg
+ - ti,davinci-chipselect
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ nand-controller@2000000 {
+ compatible = "ti,davinci-nand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0x02000000>;
+ ti,davinci-chipselect = <1>;
+ ti,davinci-mask-ale = <0>;
+ ti,davinci-mask-cle = <0>;
+ ti,davinci-mask-chipsel = <0>;
+ ti,davinci-nand-buswidth = <16>;
+ ti,davinci-ecc-mode = "hw";
+ ti,davinci-ecc-bits = <4>;
+ ti,davinci-nand-use-bbt;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot env";
+ reg = <0 0x020000>;
+ };
+ };
+ };
--
2.46.0
On Tue, Oct 08, 2024 at 09:02:45AM +0200, Marcus Folkesson wrote:
> Convert the bindings to yaml format.
>
> Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
> ---
> .../devicetree/bindings/mtd/davinci-nand.txt | 94 -----------------
> .../devicetree/bindings/mtd/ti,davinci-nand.yaml | 115 +++++++++++++++++++++
> 2 files changed, 115 insertions(+), 94 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..1263616593532e8483d556b4242b004a16620ddf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI DaVinci NAND controller
> +
> +maintainers:
> + - Marcus Folkesson <marcus.folkesson@gmail.com>
> +
> +allOf:
> + - $ref: nand-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - ti,davinci-nand
> + - ti,keystone-nand
> +
> + reg:
> + maxItems: 1
This was different in original binding and commit msg does not explain
changes. Be sure any change from pure conversion is explained in the
commit msg.
> +
> + partitions:
> + $ref: /schemas/mtd/partitions/partitions.yaml
> +
> + ti,davinci-chipselect:
> + description:
> + Number of chipselect. Indicate on the davinci_nand driver which
> + chipselect is used for accessing the nand.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3]
> +
> + ti,davinci-mask-ale:
> + description:
> + Mask for ALE. Needed for executing address phase. These offset will be
> + added to the base address for the chip select space the NAND Flash
> + device is connected to.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0x08
> +
> + ti,davinci-mask-cle:
> + description:
> + Mask for CLE. Needed for executing command phase. These offset will be
> + added to the base address for the chip select space the NAND Flash device
> + is connected to.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0x10
> +
> + ti,davinci-mask-chipsel:
> + description:
> + Mask for chipselect address. Needed to mask addresses for given
> + chipselect.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> +
> + ti,davinci-ecc-bits:
> + description: Used ECC bits.
> + enum: [1, 4]
> +
> + ti,davinci-ecc-mode:
> + description: Operation mode of the NAND ECC mode.
> + $ref: /schemas/types.yaml#/definitions/string
> + enum: [none, soft, hw, on-die]
> + deprecated: true
> +
> + ti,davinci-nand-buswidth:
> + description: Bus width to the NAND chip
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [8, 16]
> + default: 8
> + deprecated: true
> +
> + ti,davinci-nand-use-bbt:
> + type: boolean
> + description:
> + Use flash based bad block table support. OOB identifier is saved in OOB
> + area.
> + deprecated: true
> +
> +required:
> + - compatible
> + - reg
> + - ti,davinci-chipselect
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + nand-controller@2000000 {
> + compatible = "ti,davinci-nand";
> + #address-cells = <1>;
> + #size-cells = <0>;
I did not notice it last time.... but what is this? How could you have
no sizes?
> +
> + reg = <0 0x02000000>;
This is odd. Address is not 0... and size should be 0.
I don't get how it even works. For sure it is not correct.
Best regards,
Krzysztof
Krzysztof,
I'm sorry for all these iterations, it wouldn't have been necessary if I had
done my homework better. I'm not too familiar with writing these and I do
often find the descriptions unclear and not obvious.
Anyway, thank you for your patience, reviews and help.
On Tue, Oct 08, 2024 at 03:28:33PM +0200, Krzysztof Kozlowski wrote:
> On Tue, Oct 08, 2024 at 09:02:45AM +0200, Marcus Folkesson wrote:
> > Convert the bindings to yaml format.
> >
> > Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
> > ---
> > .../devicetree/bindings/mtd/davinci-nand.txt | 94 -----------------
> > .../devicetree/bindings/mtd/ti,davinci-nand.yaml | 115 +++++++++++++++++++++
> > 2 files changed, 115 insertions(+), 94 deletions(-)
> >
>
>
> > diff --git a/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..1263616593532e8483d556b4242b004a16620ddf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
> > @@ -0,0 +1,115 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: TI DaVinci NAND controller
> > +
> > +maintainers:
> > + - Marcus Folkesson <marcus.folkesson@gmail.com>
> > +
> > +allOf:
> > + - $ref: nand-controller.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - ti,davinci-nand
> > + - ti,keystone-nand
> > +
> > + reg:
> > + maxItems: 1
>
> This was different in original binding and commit msg does not explain
> changes. Be sure any change from pure conversion is explained in the
> commit msg.
Hm. Another misinterpretation from my side.
Should I use items instead? E.g.
reg:
items:
- description: |
Contains 2 offset/length values:
- offset and length for the access window.
- offset and length for accessing the AEMIF
control registers.
>
> > +
> > + partitions:
> > + $ref: /schemas/mtd/partitions/partitions.yaml
> > +
> > + ti,davinci-chipselect:
> > + description:
> > + Number of chipselect. Indicate on the davinci_nand driver which
> > + chipselect is used for accessing the nand.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1, 2, 3]
> > +
> > + ti,davinci-mask-ale:
> > + description:
> > + Mask for ALE. Needed for executing address phase. These offset will be
> > + added to the base address for the chip select space the NAND Flash
> > + device is connected to.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0x08
> > +
> > + ti,davinci-mask-cle:
> > + description:
> > + Mask for CLE. Needed for executing command phase. These offset will be
> > + added to the base address for the chip select space the NAND Flash device
> > + is connected to.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0x10
> > +
> > + ti,davinci-mask-chipsel:
> > + description:
> > + Mask for chipselect address. Needed to mask addresses for given
> > + chipselect.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0
> > +
> > + ti,davinci-ecc-bits:
> > + description: Used ECC bits.
> > + enum: [1, 4]
> > +
> > + ti,davinci-ecc-mode:
> > + description: Operation mode of the NAND ECC mode.
> > + $ref: /schemas/types.yaml#/definitions/string
> > + enum: [none, soft, hw, on-die]
> > + deprecated: true
> > +
> > + ti,davinci-nand-buswidth:
> > + description: Bus width to the NAND chip
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [8, 16]
> > + default: 8
> > + deprecated: true
> > +
> > + ti,davinci-nand-use-bbt:
> > + type: boolean
> > + description:
> > + Use flash based bad block table support. OOB identifier is saved in OOB
> > + area.
> > + deprecated: true
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - ti,davinci-chipselect
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + nand-controller@2000000 {
> > + compatible = "ti,davinci-nand";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> I did not notice it last time.... but what is this? How could you have
> no sizes?
>
> > +
> > + reg = <0 0x02000000>;
>
> This is odd. Address is not 0... and size should be 0.
>
> I don't get how it even works. For sure it is not correct.
Outch. It slipped through when I was laborating.
This was the example I wanted to get working:
```
examples:
- |
nand-controller@2000000,0 {
compatible = "ti,davinci-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x02000000 0x02000000
1 0x00000000 0x00008000>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>;
ti,davinci-mask-cle = <0>;
ti,davinci-mask-chipsel = <0>;
ti,davinci-nand-buswidth = <16>;
ti,davinci-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
ti,davinci-nand-use-bbt;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot env";
reg = <0 0x020000>;
};
};
};
```
But I'm getting the following errors:
```
.../ti,davinci-nand.example.dtb: nand-controller@2000000,0: #size-cells: 0 was expected
from schema $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
.../ti,davinci-nand.example.dtb: nand-controller@2000000,0: reg: [[0, 33554432], [33554432, 1], [0, 32768]] is too long
from schema $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
.../ti,davinci-nand.example.dtb: nand-controller@2000000,0: Unevaluated properties are not allowed ('reg' was unexpected)
from schema $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
```
The resuling 'ti,davinci-nand.example.dts' contains the following:
```
example-0 {
#address-cells = <1>;
#size-cells = <1>;
nand-controller@2000000,0 {
compatible = "ti,davinci-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x02000000 0x02000000
1 0x00000000 0x00008000>;
```
How do I set #address-cells in example-0 to 2?
I guess that is the problem.
>
> Best regards,
> Krzysztof
Thanks,
Marcus
On 14/10/2024 14:04, Marcus Folkesson wrote:
>
> Krzysztof,
>
> I'm sorry for all these iterations, it wouldn't have been necessary if I had
> done my homework better. I'm not too familiar with writing these and I do
> often find the descriptions unclear and not obvious.
> Anyway, thank you for your patience, reviews and help.
>
>
> On Tue, Oct 08, 2024 at 03:28:33PM +0200, Krzysztof Kozlowski wrote:
>> On Tue, Oct 08, 2024 at 09:02:45AM +0200, Marcus Folkesson wrote:
>>> Convert the bindings to yaml format.
>>>
>>> Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
>>> ---
>>> .../devicetree/bindings/mtd/davinci-nand.txt | 94 -----------------
>>> .../devicetree/bindings/mtd/ti,davinci-nand.yaml | 115 +++++++++++++++++++++
>>> 2 files changed, 115 insertions(+), 94 deletions(-)
>>>
>>
>>
>>> diff --git a/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
>>> new file mode 100644
>>> index 0000000000000000000000000000000000000000..1263616593532e8483d556b4242b004a16620ddf
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
>>> @@ -0,0 +1,115 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: TI DaVinci NAND controller
>>> +
>>> +maintainers:
>>> + - Marcus Folkesson <marcus.folkesson@gmail.com>
>>> +
>>> +allOf:
>>> + - $ref: nand-controller.yaml#
>>> +
>>> +properties:
>>> + compatible:
>>> + enum:
>>> + - ti,davinci-nand
>>> + - ti,keystone-nand
>>> +
>>> + reg:
>>> + maxItems: 1
>>
>> This was different in original binding and commit msg does not explain
>> changes. Be sure any change from pure conversion is explained in the
>> commit msg.
>
> Hm. Another misinterpretation from my side.
> Should I use items instead? E.g.
>
> reg:
> items:
> - description: |
> Contains 2 offset/length values:
> - offset and length for the access window.
> - offset and length for accessing the AEMIF
> control registers.
You need to list two items, so two times "- description:"
(and drop redundant parts like "offset and length" because this cannot
be anything else)
and this should be pointed out by testing, so open the example and try
to explain why it is so different than expected.
Unless, it is supposed to be one item... but how do I know? You are
looking at the device and its driver, not me.
>
>>
>>> +
>>> + partitions:
>>> + $ref: /schemas/mtd/partitions/partitions.yaml
>>> +
>>> + ti,davinci-chipselect:
>>> + description:
>>> + Number of chipselect. Indicate on the davinci_nand driver which
>>> + chipselect is used for accessing the nand.
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + enum: [0, 1, 2, 3]
>>> +
>>> + ti,davinci-mask-ale:
>>> + description:
>>> + Mask for ALE. Needed for executing address phase. These offset will be
>>> + added to the base address for the chip select space the NAND Flash
>>> + device is connected to.
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + default: 0x08
>>> +
>>> + ti,davinci-mask-cle:
>>> + description:
>>> + Mask for CLE. Needed for executing command phase. These offset will be
>>> + added to the base address for the chip select space the NAND Flash device
>>> + is connected to.
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + default: 0x10
>>> +
>>> + ti,davinci-mask-chipsel:
>>> + description:
>>> + Mask for chipselect address. Needed to mask addresses for given
>>> + chipselect.
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + default: 0
>>> +
>>> + ti,davinci-ecc-bits:
>>> + description: Used ECC bits.
>>> + enum: [1, 4]
>>> +
>>> + ti,davinci-ecc-mode:
>>> + description: Operation mode of the NAND ECC mode.
>>> + $ref: /schemas/types.yaml#/definitions/string
>>> + enum: [none, soft, hw, on-die]
>>> + deprecated: true
>>> +
>>> + ti,davinci-nand-buswidth:
>>> + description: Bus width to the NAND chip
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + enum: [8, 16]
>>> + default: 8
>>> + deprecated: true
>>> +
>>> + ti,davinci-nand-use-bbt:
>>> + type: boolean
>>> + description:
>>> + Use flash based bad block table support. OOB identifier is saved in OOB
>>> + area.
>>> + deprecated: true
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - ti,davinci-chipselect
>>> +
>>> +unevaluatedProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + nand-controller@2000000 {
>>> + compatible = "ti,davinci-nand";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>
>> I did not notice it last time.... but what is this? How could you have
>> no sizes?
>>
>>> +
>>> + reg = <0 0x02000000>;
>>
>> This is odd. Address is not 0... and size should be 0.
>>
>> I don't get how it even works. For sure it is not correct.
>
> Outch. It slipped through when I was laborating.
>
> This was the example I wanted to get working:
>
>
> ```
> examples:
> - |
> nand-controller@2000000,0 {
> compatible = "ti,davinci-nand";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0 0x02000000 0x02000000
> 1 0x00000000 0x00008000>;
But that's not what is being used. Open the DTS and look how it is
encoded there. You have unnecessary 64-bit addressing here, plus you
still have technically one item, not two. Maybe existing DTS uses it,
then it's fine, but then take DTS (and correct it if it does not define
proper tuples/items).
>
> ti,davinci-chipselect = <1>;
> ti,davinci-mask-ale = <0>;
> ti,davinci-mask-cle = <0>;
> ti,davinci-mask-chipsel = <0>;
>
> ti,davinci-nand-buswidth = <16>;
> ti,davinci-ecc-mode = "hw";
> ti,davinci-ecc-bits = <4>;
> ti,davinci-nand-use-bbt;
>
> partitions {
> compatible = "fixed-partitions";
> #address-cells = <1>;
> #size-cells = <1>;
>
> partition@0 {
> label = "u-boot env";
> reg = <0 0x020000>;
> };
> };
> };
> ```
>
>
> But I'm getting the following errors:
>
> ```
> .../ti,davinci-nand.example.dtb: nand-controller@2000000,0: #size-cells: 0 was expected
> from schema $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
> .../ti,davinci-nand.example.dtb: nand-controller@2000000,0: reg: [[0, 33554432], [33554432, 1], [0, 32768]] is too long
> from schema $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
> .../ti,davinci-nand.example.dtb: nand-controller@2000000,0: Unevaluated properties are not allowed ('reg' was unexpected)
> from schema $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
> ```
Well, obviously. That's the point of the schema. The example part is
embedded in node with some address/size cells, which might fit your case
or might not.
>
> The resuling 'ti,davinci-nand.example.dts' contains the following:
>
> ```
> example-0 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> nand-controller@2000000,0 {
> compatible = "ti,davinci-nand";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0 0x02000000 0x02000000
> 1 0x00000000 0x00008000>;
> ```
>
>
> How do I set #address-cells in example-0 to 2?
> I guess that is the problem.
You just set it... There are dozens/hundreds of schemas doing it, what
is exactly a problem here?
Best regards,
Krzysztof
Kryzstof,
On Mon, Oct 14, 2024 at 08:08:15PM +0200, Krzysztof Kozlowski wrote:
> On 14/10/2024 14:04, Marcus Folkesson wrote:
[...]
> >
> > reg:
> > items:
> > - description: |
> > Contains 2 offset/length values:
> > - offset and length for the access window.
> > - offset and length for accessing the AEMIF
> > control registers.
>
> You need to list two items, so two times "- description:"
> (and drop redundant parts like "offset and length" because this cannot
> be anything else)
>
> and this should be pointed out by testing, so open the example and try
> to explain why it is so different than expected.
>
>
> Unless, it is supposed to be one item... but how do I know? You are
> looking at the device and its driver, not me.
Ok, thank you.
I will go for:
reg:
items:
- description:
Access window
- description:
AEMIF control registers
[...]
> >
> > But I'm getting the following errors:
> >
> > ```
> > .../ti,davinci-nand.example.dtb: nand-controller@2000000,0: #size-cells: 0 was expected
> > from schema $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
> > .../ti,davinci-nand.example.dtb: nand-controller@2000000,0: reg: [[0, 33554432], [33554432, 1], [0, 32768]] is too long
> > from schema $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
> > .../ti,davinci-nand.example.dtb: nand-controller@2000000,0: Unevaluated properties are not allowed ('reg' was unexpected)
> > from schema $id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
> > ```
>
> Well, obviously. That's the point of the schema. The example part is
> embedded in node with some address/size cells, which might fit your case
> or might not.
>
> >
> > The resuling 'ti,davinci-nand.example.dts' contains the following:
> >
> > ```
> > example-0 {
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> > nand-controller@2000000,0 {
> > compatible = "ti,davinci-nand";
> > #address-cells = <1>;
> > #size-cells = <1>;
> > reg = <0 0x02000000 0x02000000
> > 1 0x00000000 0x00008000>;
> > ```
> >
> >
> > How do I set #address-cells in example-0 to 2?
> > I guess that is the problem.
>
>
>
> You just set it... There are dozens/hundreds of schemas doing it, what
> is exactly a problem here?
I think I will solve the problem by including the parent nodes.
What do you think about this?
examples:
- |
aemif: aemif@68000000 {
compatible = "ti,da850-aemif";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x68000000 0x00008000>;
ranges = <0 0 0x60000000 0x08000000
1 0 0x68000000 0x00008000>;
clocks = <&psc0 3>;
clock-names = "aemif";
clock-ranges;
cs3 {
#address-cells = <2>;
#size-cells = <1>;
clock-ranges;
ranges;
ti,cs-chipselect = <3>;
nand-controller@2000000,0 {
compatible = "ti,davinci-nand";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x02000000 0x02000000
1 0x00000000 0x00008000>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>;
ti,davinci-mask-cle = <0>;
ti,davinci-mask-chipsel = <0>;
ti,davinci-nand-buswidth = <16>;
ti,davinci-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
ti,davinci-nand-use-bbt;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot env";
reg = <0 0x020000>;
};
};
};
};
};
>
> Best regards,
> Krzysztof
>
Best regards,
Marcus Folkesson
On 18/10/2024 11:12, Marcus Folkesson wrote:
>>> ```
>>>
>>>
>>> How do I set #address-cells in example-0 to 2?
>>> I guess that is the problem.
>>
>>
>>
>> You just set it... There are dozens/hundreds of schemas doing it, what
>> is exactly a problem here?
>
> I think I will solve the problem by including the parent nodes.
Just like everyone else or some other way?
> What do you think about this?
>
> examples:
> - |
> aemif: aemif@68000000 {
> compatible = "ti,da850-aemif";
> #address-cells = <2>;
> #size-cells = <1>;
>
> reg = <0x68000000 0x00008000>;
> ranges = <0 0 0x60000000 0x08000000
> 1 0 0x68000000 0x00008000>;
> clocks = <&psc0 3>;
> clock-names = "aemif";
> clock-ranges;
That's some other way, so no, drop unrelated properties. Look how all
other bindings are doing it - you need some wrapper node.
Best regards,
Krzysztof
Hi Marcus, marcus.folkesson@gmail.com wrote on Tue, 08 Oct 2024 09:02:45 +0200: > Convert the bindings to yaml format. Impressive how legacy these descriptions are. Anyway, the conversion lgtm, so let's see what the binding maintainers think of it. Thanks, Miquèl
© 2016 - 2024 Red Hat, Inc.