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[PATCH V1 2/3] arm64: dts: qcom: sm8650: Add ICE algorithm entries

Ram Kumar Dwivedi posted 3 patches 1 month, 3 weeks ago
[PATCH V1 2/3] arm64: dts: qcom: sm8650: Add ICE algorithm entries
Posted by Ram Kumar Dwivedi 1 month, 3 weeks ago 
There are three algorithms supported for inline crypto engine:
Floor based, Static and Instantaneous algorithm.

Add ice algorithm entries and enable instantaneous algorithm
by default.

Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 9d9bbb9aca64..56a7ca6a3af4 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2590,6 +2590,25 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 			#reset-cells = <1>;
 
 			status = "disabled";
+
+			ice_cfg: ice-config {
+				alg1 {
+					alg-name = "alg1";
+					rx-alloc-percent = <60>;
+					status = "disabled";
+				};
+
+				alg2 {
+					alg-name = "alg2";
+					status = "disabled";
+				};
+
+				alg3 {
+					alg-name = "alg3";
+					num-core = <28 28 15 13>;
+					status = "ok";
+				};
+			};
 		};
 
 		ice: crypto@1d88000 {
-- 
2.46.0
Re: [PATCH V1 2/3] arm64: dts: qcom: sm8650: Add ICE algorithm entries
Posted by Krzysztof Kozlowski 1 month, 3 weeks ago 
On 05/10/2024 08:43, Ram Kumar Dwivedi wrote:
> There are three algorithms supported for inline crypto engine:
> Floor based, Static and Instantaneous algorithm.
> 
> Add ice algorithm entries and enable instantaneous algorithm
> by default.
> 
> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
> Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8650.dtsi | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 9d9bbb9aca64..56a7ca6a3af4 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2590,6 +2590,25 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  			#reset-cells = <1>;
>  
>  			status = "disabled";
> +
> +			ice_cfg: ice-config {
> +				alg1 {
> +					alg-name = "alg1";
> +					rx-alloc-percent = <60>;
> +					status = "disabled";
> +				};
> +
> +				alg2 {
> +					alg-name = "alg2";
> +					status = "disabled";
> +				};
> +
> +				alg3 {
> +					alg-name = "alg3";
> +					num-core = <28 28 15 13>;
> +					status = "ok";

NAK. This has so many issues... First, describes OS policy. Second,
there is no "ok".

Best regards,
Krzysztof
Re: [PATCH V1 2/3] arm64: dts: qcom: sm8650: Add ICE algorithm entries
Posted by Ram Kumar Dwivedi 4 weeks, 1 day ago 

On 06-Oct-24 2:02 PM, Krzysztof Kozlowski wrote:
> On 05/10/2024 08:43, Ram Kumar Dwivedi wrote:
>> There are three algorithms supported for inline crypto engine:
>> Floor based, Static and Instantaneous algorithm.
>>
>> Add ice algorithm entries and enable instantaneous algorithm
>> by default.
>>
>> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
>> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
>> Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/sm8650.dtsi | 19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> index 9d9bbb9aca64..56a7ca6a3af4 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> @@ -2590,6 +2590,25 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>  			#reset-cells = <1>;
>>  
>>  			status = "disabled";
>> +
>> +			ice_cfg: ice-config {
>> +				alg1 {
>> +					alg-name = "alg1";
>> +					rx-alloc-percent = <60>;
>> +					status = "disabled";
>> +				};
>> +
>> +				alg2 {
>> +					alg-name = "alg2";
>> +					status = "disabled";
>> +				};
>> +
>> +				alg3 {
>> +					alg-name = "alg3";
>> +					num-core = <28 28 15 13>;
>> +					status = "ok";
> 
> NAK. This has so many issues... First, describes OS policy. Second,
> there is no "ok".
> 
Hi Krzysztof,
	I have updated the status to "okay" in latest patchset and updated the alg-name with actual allocator name.
	I have already mentioned default allocator as instantaneous. Sorry, I did not understand OS policy comment, could you please explain?
Thanks,
Ram.

> Best regards,
> Krzysztof
>
Re: [PATCH V1 2/3] arm64: dts: qcom: sm8650: Add ICE algorithm entries
Posted by Krzysztof Kozlowski 4 weeks, 1 day ago 
On 29/10/2024 12:06, Ram Kumar Dwivedi wrote:
> 
> 
> On 06-Oct-24 2:02 PM, Krzysztof Kozlowski wrote:
>> On 05/10/2024 08:43, Ram Kumar Dwivedi wrote:
>>> There are three algorithms supported for inline crypto engine:
>>> Floor based, Static and Instantaneous algorithm.
>>>
>>> Add ice algorithm entries and enable instantaneous algorithm
>>> by default.
>>>
>>> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
>>> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
>>> Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/sm8650.dtsi | 19 +++++++++++++++++++
>>>  1 file changed, 19 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> index 9d9bbb9aca64..56a7ca6a3af4 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> @@ -2590,6 +2590,25 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>  			#reset-cells = <1>;
>>>  
>>>  			status = "disabled";
>>> +
>>> +			ice_cfg: ice-config {
>>> +				alg1 {
>>> +					alg-name = "alg1";
>>> +					rx-alloc-percent = <60>;
>>> +					status = "disabled";
>>> +				};
>>> +
>>> +				alg2 {
>>> +					alg-name = "alg2";
>>> +					status = "disabled";
>>> +				};
>>> +
>>> +				alg3 {
>>> +					alg-name = "alg3";
>>> +					num-core = <28 28 15 13>;
>>> +					status = "ok";
>>
>> NAK. This has so many issues... First, describes OS policy. Second,
>> there is no "ok".
>>
> Hi Krzysztof,
> 	I have updated the status to "okay" in latest patchset

Still no. Why this node needs it?

> and updated the alg-name with actual allocator name.

Please wrap your replies according to mailing list style.

But anyway, all your algs sound like OS policy.


> 	I have already mentioned default allocator as instantaneous. Sorry, I did not understand OS policy comment, could you please explain?

This looks like OS policy, OS choice. DT does not describe such things.

Best regards,
Krzysztof

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