KVM: arm64: Provide guest support for GCS

[PATCH v14 4/5] KVM: arm64: Set PSTATE.EXLOCK when entering an exception

Posted by Mark Brown 1 month, 3 weeks ago

As per DDI 0487 RWTXBY we need to manage PSTATE.EXLOCK when entering an
exception, when the exception is entered from a lower EL the bit is cleared
while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN.
Implement this behaviour in enter_exception64().

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/uapi/asm/ptrace.h |  2 ++
 arch/arm64/kvm/hyp/exception.c       | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
index 0f39ba4f3efd4a8760f0fca0fbf1a2563b191c7d..9987957f4f7137bf107653b817885bb976853a83 100644
--- a/arch/arm64/include/uapi/asm/ptrace.h
+++ b/arch/arm64/include/uapi/asm/ptrace.h
@@ -37,6 +37,7 @@
 #define PSR_MODE_EL3t	0x0000000c
 #define PSR_MODE_EL3h	0x0000000d
 #define PSR_MODE_MASK	0x0000000f
+#define PSR_EL_MASK	0x0000000c
 
 /* AArch32 CPSR bits */
 #define PSR_MODE32_BIT		0x00000010
@@ -56,6 +57,7 @@
 #define PSR_C_BIT	0x20000000
 #define PSR_Z_BIT	0x40000000
 #define PSR_N_BIT	0x80000000
+#define PSR_EXLOCK_BIT 0x400000000
 
 #define PSR_BTYPE_SHIFT		10
 
diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c
index 424a5107cddb5e1cdd75ef3581adef03aaadabb7..0d41b9b75cf83250b2c0d20cd82c153869efb0e4 100644
--- a/arch/arm64/kvm/hyp/exception.c
+++ b/arch/arm64/kvm/hyp/exception.c
@@ -160,6 +160,16 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode,
 	// PSTATE.BTYPE is set to zero upon any exception to AArch64
 	// See ARM DDI 0487E.a, pages D1-2293 to D1-2294.
 
+	// PSTATE.EXLOCK is set to 0 upon any exception to a higher
+	// EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same
+	// exception level.  See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a.
+	if (kvm_has_gcs(vcpu->kvm) &&
+	    (target_mode & PSR_EL_MASK) == (mode & PSR_EL_MASK)) {
+		u64 gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL1);
+		if (gcscr & GCSCR_ELx_EXLOCKEN)
+			new |= PSR_EXLOCK_BIT;
+	}
+
 	new |= PSR_D_BIT;
 	new |= PSR_A_BIT;
 	new |= PSR_I_BIT;

-- 
2.39.2

Re: [PATCH v14 4/5] KVM: arm64: Set PSTATE.EXLOCK when entering an exception

Posted by Marc Zyngier 1 month, 3 weeks ago

On Sat, 05 Oct 2024 11:37:31 +0100,
Mark Brown <broonie@kernel.org> wrote:
> 
> As per DDI 0487 RWTXBY we need to manage PSTATE.EXLOCK when entering an
> exception, when the exception is entered from a lower EL the bit is cleared
> while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN.
> Implement this behaviour in enter_exception64().
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/uapi/asm/ptrace.h |  2 ++
>  arch/arm64/kvm/hyp/exception.c       | 10 ++++++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
> index 0f39ba4f3efd4a8760f0fca0fbf1a2563b191c7d..9987957f4f7137bf107653b817885bb976853a83 100644
> --- a/arch/arm64/include/uapi/asm/ptrace.h
> +++ b/arch/arm64/include/uapi/asm/ptrace.h
> @@ -37,6 +37,7 @@
>  #define PSR_MODE_EL3t	0x0000000c
>  #define PSR_MODE_EL3h	0x0000000d
>  #define PSR_MODE_MASK	0x0000000f
> +#define PSR_EL_MASK	0x0000000c
>  
>  /* AArch32 CPSR bits */
>  #define PSR_MODE32_BIT		0x00000010
> @@ -56,6 +57,7 @@
>  #define PSR_C_BIT	0x20000000
>  #define PSR_Z_BIT	0x40000000
>  #define PSR_N_BIT	0x80000000
> +#define PSR_EXLOCK_BIT 0x400000000
>  
>  #define PSR_BTYPE_SHIFT		10
>  
> diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c
> index 424a5107cddb5e1cdd75ef3581adef03aaadabb7..0d41b9b75cf83250b2c0d20cd82c153869efb0e4 100644
> --- a/arch/arm64/kvm/hyp/exception.c
> +++ b/arch/arm64/kvm/hyp/exception.c
> @@ -160,6 +160,16 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode,
>  	// PSTATE.BTYPE is set to zero upon any exception to AArch64
>  	// See ARM DDI 0487E.a, pages D1-2293 to D1-2294.
>  
> +	// PSTATE.EXLOCK is set to 0 upon any exception to a higher
> +	// EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same
> +	// exception level.  See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a.
> +	if (kvm_has_gcs(vcpu->kvm) &&
> +	    (target_mode & PSR_EL_MASK) == (mode & PSR_EL_MASK)) {
> +		u64 gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL1);

No, please. This only works by luck when a guest has AArch32 EL0, and
creates more havoc on a NV guest. In general, this PSR_EL_MASK creates
more problem than anything else, and doesn't fit the rest of the code.

So this needs to:
- explicitly only apply to exceptions from AArch64
- handle exception from EL2, since this helper already deals with that

The latter point of course means introducing GCSCR_EL2 (and everything
that depends on it, such as the trap handling).

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v14 4/5] KVM: arm64: Set PSTATE.EXLOCK when entering an exception

Posted by Mark Brown 1 month, 3 weeks ago

On Sat, Oct 05, 2024 at 01:36:09PM +0100, Marc Zyngier wrote:
> Mark Brown <broonie@kernel.org> wrote:

> > +	// PSTATE.EXLOCK is set to 0 upon any exception to a higher
> > +	// EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same
> > +	// exception level.  See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a.
> > +	if (kvm_has_gcs(vcpu->kvm) &&
> > +	    (target_mode & PSR_EL_MASK) == (mode & PSR_EL_MASK)) {
> > +		u64 gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL1);

> No, please. This only works by luck when a guest has AArch32 EL0, and
> creates more havoc on a NV guest. In general, this PSR_EL_MASK creates
> more problem than anything else, and doesn't fit the rest of the code.

You say luck, I say careful architecture definition but sure.

> So this needs to:
> - explicitly only apply to exceptions from AArch64
> - handle exception from EL2, since this helper already deals with that

> The latter point of course means introducing GCSCR_EL2 (and everything
> that depends on it, such as the trap handling).

For clarity, which trap handling specifically?

Re: [PATCH v14 4/5] KVM: arm64: Set PSTATE.EXLOCK when entering an exception

Posted by Marc Zyngier 1 month, 3 weeks ago

On Sat, 05 Oct 2024 15:14:21 +0100,
Mark Brown <broonie@kernel.org> wrote:
> 
> On Sat, Oct 05, 2024 at 01:36:09PM +0100, Marc Zyngier wrote:
> > Mark Brown <broonie@kernel.org> wrote:
> 
> > > +	// PSTATE.EXLOCK is set to 0 upon any exception to a higher
> > > +	// EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same
> > > +	// exception level.  See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a.
> > > +	if (kvm_has_gcs(vcpu->kvm) &&
> > > +	    (target_mode & PSR_EL_MASK) == (mode & PSR_EL_MASK)) {
> > > +		u64 gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL1);
> 
> > No, please. This only works by luck when a guest has AArch32 EL0, and
> > creates more havoc on a NV guest. In general, this PSR_EL_MASK creates
> > more problem than anything else, and doesn't fit the rest of the code.
> 
> You say luck, I say careful architecture definition but sure.

I wasn't talking about the architecture, but sure.

> 
> > So this needs to:
> > - explicitly only apply to exceptions from AArch64
> > - handle exception from EL2, since this helper already deals with that
> 
> > The latter point of course means introducing GCSCR_EL2 (and everything
> > that depends on it, such as the trap handling).
> 
> For clarity, which trap handling specifically?

All the traps described in the GCSCR_EL2 documentation -- I see two
control bits described in K.a, all of which needs to be propagated and
their effects handled. Similarly, GCSPR_EL2 needs to be defined.

	M.

-- 
Without deviation from the norm, progress is not possible.