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[PATCH] arm64: dts: renesas: r9a09g057: Add OPP table

Prabhakar posted 1 patch 1 month, 3 weeks ago
There is a newer version of this series
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
[PATCH] arm64: dts: renesas: r9a09g057: Add OPP table
Posted by Prabhakar 1 month, 3 weeks ago 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add OPP table for RZ/V2H(P) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Note, this patch depends on [0] for frequency scaling to work.

[0] https://lore.kernel.org/all/20240918135957.290101-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 1ad5a1b6917f..396c95bc1b4e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -20,6 +20,39 @@ audio_extal_clk: audio-clk {
 		clock-frequency = <0>;
 	};
 
+	/*
+	 * The default cluster table is based on the assumption that the PLLCA55 clock
+	 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
+	 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
+	 * clocked to 1.8GHz as well). The table below should be overridden in the board
+	 * DTS based on the PLLCA55 clock frequency.
+	 */
+	cluster0_opp: opp-table-0 {
+		compatible = "operating-points-v2";
+
+		opp-1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-850000000 {
+			opp-hz = /bits/ 64 <850000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-425000000 {
+			opp-hz = /bits/ 64 <425000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-212500000 {
+			opp-hz = /bits/ 64 <212500000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -30,6 +63,8 @@ cpu0: cpu@0 {
 			device_type = "cpu";
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu@100 {
@@ -38,6 +73,8 @@ cpu1: cpu@100 {
 			device_type = "cpu";
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu2: cpu@200 {
@@ -46,6 +83,8 @@ cpu2: cpu@200 {
 			device_type = "cpu";
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu3: cpu@300 {
@@ -54,6 +93,8 @@ cpu3: cpu@300 {
 			device_type = "cpu";
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		L3_CA55: cache-controller-0 {
-- 
2.43.0
Re: [PATCH] arm64: dts: renesas: r9a09g057: Add OPP table
Posted by Geert Uytterhoeven 1 month, 2 weeks ago 
Hi Prabhakar,

On Fri, Oct 4, 2024 at 3:31 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add OPP table for RZ/V2H(P) SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk {
>                 clock-frequency = <0>;
>         };
>
> +       /*
> +        * The default cluster table is based on the assumption that the PLLCA55 clock
> +        * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
> +        * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
> +        * clocked to 1.8GHz as well). The table below should be overridden in the board
> +        * DTS based on the PLLCA55 clock frequency.
> +        */
> +       cluster0_opp: opp-table-0 {
> +               compatible = "operating-points-v2";
> +
> +               opp-1700000000 {
> +                       opp-hz = /bits/ 64 <1700000000>;
> +                       opp-microvolt = <900000>;
> +                       clock-latency-ns = <300000>;
> +               };
> +               opp-850000000 {
> +                       opp-hz = /bits/ 64 <850000000>;
> +                       opp-microvolt = <900000>;

According to Table 10.1-2 ("Recommended Operating Range"), this should
be 800000 for this and all operating points below.

> +                       clock-latency-ns = <300000>;
> +               };
> +               opp-425000000 {
> +                       opp-hz = /bits/ 64 <425000000>;
> +                       opp-microvolt = <900000>;
> +                       clock-latency-ns = <300000>;
> +               };
> +               opp-212500000 {
> +                       opp-hz = /bits/ 64 <212500000>;
> +                       opp-microvolt = <900000>;
> +                       clock-latency-ns = <300000>;
> +                       opp-suspend;
> +               };
> +       };

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Re: [PATCH] arm64: dts: renesas: r9a09g057: Add OPP table
Posted by Lad, Prabhakar 1 month, 2 weeks ago 
Hi Geert,

Thank you for the review.

On Tue, Oct 8, 2024 at 11:08 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, Oct 4, 2024 at 3:31 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add OPP table for RZ/V2H(P) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk {
> >                 clock-frequency = <0>;
> >         };
> >
> > +       /*
> > +        * The default cluster table is based on the assumption that the PLLCA55 clock
> > +        * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
> > +        * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
> > +        * clocked to 1.8GHz as well). The table below should be overridden in the board
> > +        * DTS based on the PLLCA55 clock frequency.
> > +        */
> > +       cluster0_opp: opp-table-0 {
> > +               compatible = "operating-points-v2";
> > +
> > +               opp-1700000000 {
> > +                       opp-hz = /bits/ 64 <1700000000>;
> > +                       opp-microvolt = <900000>;
> > +                       clock-latency-ns = <300000>;
> > +               };
> > +               opp-850000000 {
> > +                       opp-hz = /bits/ 64 <850000000>;
> > +                       opp-microvolt = <900000>;
>
> According to Table 10.1-2 ("Recommended Operating Range"), this should
> be 800000 for this and all operating points below.
>
Agreed, I had missed that. I added the voltage level based on the
schematic VDD09_CA55

Cheers,
Prabhakar

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