From: "SkyLake.Huang" <skylake.huang@mediatek.com>
This patch shrinks mtk-ge-soc.c line wrapping to 80 characters.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
drivers/net/phy/mediatek/mtk-ge-soc.c | 67 +++++++++++++++++----------
1 file changed, 42 insertions(+), 25 deletions(-)
diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c
index 26c2183..cb6838b 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -295,7 +295,8 @@ static int cal_cycle(struct phy_device *phydev, int devad,
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
MTK_PHY_RG_AD_CAL_CLK, reg_val,
reg_val & MTK_PHY_DA_CAL_CLK, 500,
- ANALOG_INTERNAL_OPERATION_MAX_US, false);
+ ANALOG_INTERNAL_OPERATION_MAX_US,
+ false);
if (ret) {
phydev_err(phydev, "Calibration cycle timeout\n");
return ret;
@@ -304,7 +305,7 @@ static int cal_cycle(struct phy_device *phydev, int devad,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
MTK_PHY_DA_CALIN_FLAG);
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
- MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
+ MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
return ret;
@@ -394,38 +395,46 @@ static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
}
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
- MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
+ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
+ (buf[0] + bias[0]) << 10);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
- MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
+ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
+ (buf[0] + bias[2]) << 10);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
- MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
+ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
+ (buf[1] + bias[4]) << 8);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
- MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
+ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
+ (buf[1] + bias[6]) << 8);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
- MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
+ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
+ (buf[2] + bias[8]) << 8);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
- MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
+ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
+ (buf[2] + bias[10]) << 8);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
- MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
+ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
+ (buf[3] + bias[12]) << 8);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
- MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
+ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
+ (buf[3] + bias[14]) << 8);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
@@ -616,7 +625,8 @@ static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
goto restore;
/* We calibrate TX-VCM in different logic. Check upper index and then
- * lower index. If this calibration is valid, apply lower index's result.
+ * lower index. If this calibration is valid, apply lower index's
+ * result.
*/
ret = upper_ret - lower_ret;
if (ret == 1) {
@@ -645,7 +655,8 @@ static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
} else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
lower_ret == 0) {
ret = 0;
- phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
+ phydev_warn(phydev,
+ "TX-VCM SW cal result at high margin 0x%x\n",
upper_idx);
} else {
ret = -EINVAL;
@@ -749,7 +760,8 @@ static void mt7981_phy_finetune(struct phy_device *phydev)
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ MTK_PHY_TR_OPEN_LOOP_EN_MASK |
+ MTK_PHY_LPF_X_AVERAGE_MASK,
BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
/* rg_tr_lpf_cnt_val = 512 */
@@ -818,7 +830,8 @@ static void mt7988_phy_finetune(struct phy_device *phydev)
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ MTK_PHY_TR_OPEN_LOOP_EN_MASK |
+ MTK_PHY_LPF_X_AVERAGE_MASK,
BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
/* rg_tr_lpf_cnt_val = 1023 */
@@ -930,7 +943,8 @@ static void mt798x_phy_eee(struct phy_device *phydev)
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
- __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
+ __phy_modify(phydev, MTK_PHY_LPI_REG_14,
+ MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
__phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
@@ -940,7 +954,8 @@ static void mt798x_phy_eee(struct phy_device *phydev)
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
+ 0xff));
}
static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
@@ -1119,14 +1134,15 @@ static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
MTK_GPHY_LED_ON_MASK, (value != LED_OFF));
}
-static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
- BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
- BIT(TRIGGER_NETDEV_LINK) |
- BIT(TRIGGER_NETDEV_LINK_10) |
- BIT(TRIGGER_NETDEV_LINK_100) |
- BIT(TRIGGER_NETDEV_LINK_1000) |
- BIT(TRIGGER_NETDEV_RX) |
- BIT(TRIGGER_NETDEV_TX));
+static const unsigned long supported_triggers =
+ (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
+ BIT(TRIGGER_NETDEV_LINK) |
+ BIT(TRIGGER_NETDEV_LINK_10) |
+ BIT(TRIGGER_NETDEV_LINK_100) |
+ BIT(TRIGGER_NETDEV_LINK_1000) |
+ BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_TX));
static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
unsigned long rules)
@@ -1189,7 +1205,8 @@ static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
/* Only now setup pinctrl to avoid bogus blinking */
pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
if (IS_ERR(pinctrl))
- dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
+ dev_err(&phydev->mdio.bus->dev,
+ "Failed to setup PHY LED pinctrl\n");
return 0;
}
--
2.45.2Hi,
On Fri, Oct 04, 2024 at 06:24:12PM +0800, Sky Huang wrote:
> diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c
> index 26c2183..cb6838b 100644
> --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
> +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
> @@ -295,7 +295,8 @@ static int cal_cycle(struct phy_device *phydev, int devad,
> ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
> MTK_PHY_RG_AD_CAL_CLK, reg_val,
> reg_val & MTK_PHY_DA_CAL_CLK, 500,
> - ANALOG_INTERNAL_OPERATION_MAX_US, false);
> + ANALOG_INTERNAL_OPERATION_MAX_US,
> + false);
This is fine.
> if (ret) {
> phydev_err(phydev, "Calibration cycle timeout\n");
> return ret;
> @@ -304,7 +305,7 @@ static int cal_cycle(struct phy_device *phydev, int devad,
> phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
> MTK_PHY_DA_CALIN_FLAG);
> ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
> - MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
> + MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
Before cleaning this up, please first make it propagate any error code
correctly (a bug fix):
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
if (ret < 0)
return ret;
ret >>= MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
and then you won't need to change it in this patch. A better solution to
the shift would be to look at FIELD_GET().
> phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
>
> return ret;
> @@ -394,38 +395,46 @@ static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
> }
>
> phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
> - MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
> + MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
> + (buf[0] + bias[0]) << 10);
Another cleanup would be to use FIELD_PREP() for these.
> -static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
> - BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
> - BIT(TRIGGER_NETDEV_LINK) |
> - BIT(TRIGGER_NETDEV_LINK_10) |
> - BIT(TRIGGER_NETDEV_LINK_100) |
> - BIT(TRIGGER_NETDEV_LINK_1000) |
> - BIT(TRIGGER_NETDEV_RX) |
> - BIT(TRIGGER_NETDEV_TX));
> +static const unsigned long supported_triggers =
> + (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
> + BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
> + BIT(TRIGGER_NETDEV_LINK) |
> + BIT(TRIGGER_NETDEV_LINK_10) |
> + BIT(TRIGGER_NETDEV_LINK_100) |
> + BIT(TRIGGER_NETDEV_LINK_1000) |
> + BIT(TRIGGER_NETDEV_RX) |
> + BIT(TRIGGER_NETDEV_TX));
The outer parens are unnecessary, and thus could be removed.
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
On Fri, 2024-10-04 at 13:07 +0100, Russell King (Oracle) wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> Hi,
>
> On Fri, Oct 04, 2024 at 06:24:12PM +0800, Sky Huang wrote:
> > diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c
> b/drivers/net/phy/mediatek/mtk-ge-soc.c
> > index 26c2183..cb6838b 100644
> > --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
> > +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
> > @@ -295,7 +295,8 @@ static int cal_cycle(struct phy_device *phydev,
> int devad,
> > ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
> > MTK_PHY_RG_AD_CAL_CLK, reg_val,
> > reg_val & MTK_PHY_DA_CAL_CLK, 500,
> > -ANALOG_INTERNAL_OPERATION_MAX_US, false);
> > +ANALOG_INTERNAL_OPERATION_MAX_US,
> > +false);
>
> This is fine.
>
> > if (ret) {
> > phydev_err(phydev, "Calibration cycle timeout\n");
> > return ret;
> > @@ -304,7 +305,7 @@ static int cal_cycle(struct phy_device *phydev,
> int devad,
> > phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
> > MTK_PHY_DA_CALIN_FLAG);
> > ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP)
> >>
> > - MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
> > + MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
>
> Before cleaning this up, please first make it propagate any error
> code
> correctly (a bug fix):
>
> ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
> if (ret < 0)
> return ret;
>
> ret >>= MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
>
> and then you won't need to change it in this patch. A better solution
> to
> the shift would be to look at FIELD_GET().
>
> > phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
> >
> > return ret;
> > @@ -394,38 +395,46 @@ static int tx_amp_fill_result(struct
> phy_device *phydev, u16 *buf)
> > }
> >
> > phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
> > - MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
> > + MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
> > + (buf[0] + bias[0]) << 10);
>
> Another cleanup would be to use FIELD_PREP() for these.
>
> > -static const unsigned long supported_triggers =
> (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
> > - BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
> > - BIT(TRIGGER_NETDEV_LINK) |
> > - BIT(TRIGGER_NETDEV_LINK_10) |
> > - BIT(TRIGGER_NETDEV_LINK_100) |
> > - BIT(TRIGGER_NETDEV_LINK_1000) |
> > - BIT(TRIGGER_NETDEV_RX) |
> > - BIT(TRIGGER_NETDEV_TX));
> > +static const unsigned long supported_triggers =
> > +(BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
> > + BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
> > + BIT(TRIGGER_NETDEV_LINK) |
> > + BIT(TRIGGER_NETDEV_LINK_10) |
> > + BIT(TRIGGER_NETDEV_LINK_100) |
> > + BIT(TRIGGER_NETDEV_LINK_1000) |
> > + BIT(TRIGGER_NETDEV_RX) |
> > + BIT(TRIGGER_NETDEV_TX));
>
> The outer parens are unnecessary, and thus could be removed.
>
> Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
Thanks. I think I'll isolate this patch and send another cleanup patch
for mediatek-ge-soc.c first.
BRs,
Sky
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