Sophgo SG2044 has a new version of T-HEAD C920, which implement
a fully featured ACLINT device. This ACLINT has an extra SSWI
field to support fast S-mode IPI.
Add necessary compatible string for the T-HEAD ACLINT sswi device.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
.../thead,c900-aclint-sswi.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
new file mode 100644
index 000000000000..0106fbf3ea1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device
+
+maintainers:
+ - Inochi Amaoto <inochiama@outlook.com>
+
+description:
+ The SSWI device is a part of the riscv ACLINT device. It provides
+ supervisor-level IPI functionality for a set of HARTs on a RISC-V
+ platform. It provides a register to set an IPI (SETSSIP) for each
+ HART connected to the SSWI device.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - sophgo,sg2044-aclint-sswi
+ - const: thead,c900-aclint-sswi
+
+ reg:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 0
+
+ interrupt-controller: true
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4095
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#interrupt-cells"
+ - interrupt-controller
+ - interrupts-extended
+
+examples:
+ - |
+ interrupt-controller@94000000 {
+ compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
+ reg = <0x94000000 0x00004000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu1intc 1>,
+ <&cpu2intc 1>,
+ <&cpu3intc 1>,
+ <&cpu4intc 1>;
+ };
+...
--
2.46.2On Fri, Oct 04, 2024 at 04:05:55PM +0800, Inochi Amaoto wrote: > Sophgo SG2044 has a new version of T-HEAD C920, which implement > a fully featured ACLINT device. This ACLINT has an extra SSWI > field to support fast S-mode IPI. > > Add necessary compatible string for the T-HEAD ACLINT sswi device. > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > --- > .../thead,c900-aclint-sswi.yaml | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > new file mode 100644 > index 000000000000..0106fbf3ea1f > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device > + > +maintainers: > + - Inochi Amaoto <inochiama@outlook.com> > + > +description: > + The SSWI device is a part of the riscv ACLINT device. It provides > + supervisor-level IPI functionality for a set of HARTs on a RISC-V > + platform. It provides a register to set an IPI (SETSSIP) for each > + HART connected to the SSWI device. If it is part of the aclint, why should it have a separate node, rather than be part of the existing aclint node as a third reg property?
On Fri, Oct 04, 2024 at 04:44:22PM +0100, Conor Dooley wrote: > On Fri, Oct 04, 2024 at 04:05:55PM +0800, Inochi Amaoto wrote: > > Sophgo SG2044 has a new version of T-HEAD C920, which implement > > a fully featured ACLINT device. This ACLINT has an extra SSWI > > field to support fast S-mode IPI. > > > > Add necessary compatible string for the T-HEAD ACLINT sswi device. > > > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > > --- > > .../thead,c900-aclint-sswi.yaml | 58 +++++++++++++++++++ > > 1 file changed, 58 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > > new file mode 100644 > > index 000000000000..0106fbf3ea1f > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > > @@ -0,0 +1,58 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device > > + > > +maintainers: > > + - Inochi Amaoto <inochiama@outlook.com> > > + > > +description: > > + The SSWI device is a part of the riscv ACLINT device. It provides > > + supervisor-level IPI functionality for a set of HARTs on a RISC-V > > + platform. It provides a register to set an IPI (SETSSIP) for each > > + HART connected to the SSWI device. > > If it is part of the aclint, why should it have a separate node, rather > than be part of the existing aclint node as a third reg property? For aclint, the current nodes that have documented are mswi and mtime. Since the mtime is a M-mode time source, it is not suitable to add the sswi reg into this device. For mswi, it is OK to add a sswi reg, but this will cause problem while checking "interrupt-extend". Do we just double the maxItem? Or just left it unchanged? Another reason to add it as a separate node is that the draft says sswi can be multiple. If we add this device by adding reg. It will be hard if we have multiple sswi devices but one mswi device. Regard, Inochi
On Sat, Oct 05, 2024 at 08:46:37AM +0800, Inochi Amaoto wrote: > On Fri, Oct 04, 2024 at 04:44:22PM +0100, Conor Dooley wrote: > > On Fri, Oct 04, 2024 at 04:05:55PM +0800, Inochi Amaoto wrote: > > > Sophgo SG2044 has a new version of T-HEAD C920, which implement > > > a fully featured ACLINT device. This ACLINT has an extra SSWI > > > field to support fast S-mode IPI. > > > > > > Add necessary compatible string for the T-HEAD ACLINT sswi device. > > > > > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > > > --- > > > .../thead,c900-aclint-sswi.yaml | 58 +++++++++++++++++++ > > > 1 file changed, 58 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > > > new file mode 100644 > > > index 000000000000..0106fbf3ea1f > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml > > > @@ -0,0 +1,58 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device > > > + > > > +maintainers: > > > + - Inochi Amaoto <inochiama@outlook.com> > > > + > > > +description: > > > + The SSWI device is a part of the riscv ACLINT device. It provides > > > + supervisor-level IPI functionality for a set of HARTs on a RISC-V > > > + platform. It provides a register to set an IPI (SETSSIP) for each > > > + HART connected to the SSWI device. > > > > If it is part of the aclint, why should it have a separate node, rather > > than be part of the existing aclint node as a third reg property? > > For aclint, the current nodes that have documented are mswi and mtime. > Since the mtime is a M-mode time source, it is not suitable to add the > sswi reg into this device. For mswi, it is OK to add a sswi reg, but > this will cause problem while checking "interrupt-extend". Do we just > double the maxItem? Or just left it unchanged? > > Another reason to add it as a separate node is that the draft says > sswi can be multiple. If we add this device by adding reg. It will be > hard if we have multiple sswi devices but one mswi device. Ah, I see we do indeed have 2 devices already for the aclint, one for mswi and mtimer.
© 2016 - 2024 Red Hat, Inc.