[v2] pinctrl: s32: add missing pins and an S32G3 compatible

[PATCH v2 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver

Posted by Andrei Stefanescu 1 month, 3 weeks ago

The SIUL2 hardware module is also integrated into the S32G3 SoC. Add
another compatible for it.

Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>
---
 .../bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml         | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
index a24286e4def6..cff766c2f03b 100644
--- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
@@ -25,8 +25,12 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - nxp,s32g2-siul2-pinctrl
+    oneOf:
+      - enum:
+          - nxp,s32g2-siul2-pinctrl
+      - items:
+          - const: nxp,s32g3-siul2-pinctrl
+          - const: nxp,s32g2-siul2-pinctrl
 
   reg:
     description: |
-- 
2.45.2

Re: [PATCH v2 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver

Posted by Conor Dooley 1 month, 3 weeks ago

On Wed, Oct 02, 2024 at 04:59:19PM +0300, Andrei Stefanescu wrote:
> The SIUL2 hardware module is also integrated into the S32G3 SoC. Add
> another compatible for it.
> 
> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>

I'm not convinced that the representation here is correct for the
GPIO on these devices. See:
https://lore.kernel.org/all/20240926143122.1385658-3-andrei.stefanescu@oss.nxp.com/
Since GPIO and pinctrl share the same regions, that lack of conviction
extends to the pinctrl. I don't think adding another compatible here is
right, when I am already of the opinion that the binding is wrong for
the existing one.

> ---
>  .../bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml         | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
> index a24286e4def6..cff766c2f03b 100644
> --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
> @@ -25,8 +25,12 @@ description: |
>  
>  properties:
>    compatible:
> -    enum:
> -      - nxp,s32g2-siul2-pinctrl
> +    oneOf:
> +      - enum:
> +          - nxp,s32g2-siul2-pinctrl
> +      - items:
> +          - const: nxp,s32g3-siul2-pinctrl
> +          - const: nxp,s32g2-siul2-pinctrl
>  
>    reg:
>      description: |
> -- 
> 2.45.2
>

Re: [PATCH v2 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver

Posted by Andrei Stefanescu 1 month, 3 weeks ago

Hi Conor,

Thank you for reviewing this!

On 02/10/2024 18:02, Conor Dooley wrote:
> On Wed, Oct 02, 2024 at 04:59:19PM +0300, Andrei Stefanescu wrote:
>> The SIUL2 hardware module is also integrated into the S32G3 SoC. Add
>> another compatible for it.
>>
>> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>
> 
> I'm not convinced that the representation here is correct for the
> GPIO on these devices. See:
> https://lore.kernel.org/all/20240926143122.1385658-3-andrei.stefanescu@oss.nxp.com/
> Since GPIO and pinctrl share the same regions, that lack of conviction
> extends to the pinctrl. I don't think adding another compatible here is
> right, when I am already of the opinion that the binding is wrong for
> the existing one.

I will convert the SIUL2 GPIO driver from my other patch series(the one
you mentioned) and merge it with the existing SIUL2 pinctrl driver.
Therefore, the unified pinctrl&GPIO will use the existing pinctrl
compatible.

I also considered the syscon&simple-mfd approach but it is harder
to implement because:
- the memory regions for the two SIUL2 modules are not next to each other
  and cannot be grouped together
- some registers in SIUL2 are 32bit wide and some are 16bit wide

The combined GPIO&pinctrl driver will have 4 memory resources:
- SIUL2_0 32 bit registers (used for pinmux&pinconf)
- SIUL2_0 16 bit registers (used for setting/getting the GPIO
			    output/input value)
- SIUL2_1 32 bit registers (same as SIUL2_0 + interrupt related registers)
- SIUL2_1 16 bit registers (same as SIUL2_0)

Would that be ok?

Best regards,
Andrei

> 
>> ---
>>  .../bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml         | 8 ++++++--
>>  1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
>> index a24286e4def6..cff766c2f03b 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
>> +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
>> @@ -25,8 +25,12 @@ description: |
>>  
>>  properties:
>>    compatible:
>> -    enum:
>> -      - nxp,s32g2-siul2-pinctrl
>> +    oneOf:
>> +      - enum:
>> +          - nxp,s32g2-siul2-pinctrl
>> +      - items:
>> +          - const: nxp,s32g3-siul2-pinctrl
>> +          - const: nxp,s32g2-siul2-pinctrl
>>  
>>    reg:
>>      description: |
>> -- 
>> 2.45.2
>>