Add PCIe node and the associated PHY node.
Individual board device tree should enable the nodes as needed.
Signed-off-by: Fei Shao <fshao@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 62 ++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 10195a4e4e9d..9431f3c5c228 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1763,6 +1763,53 @@ xhci0: usb@112b0000 {
status = "disabled";
};
+ pcie: pcie@112f0000 {
+ compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie";
+ reg = <0 0x112f0000 0 0x2000>;
+ reg-names = "pcie-mac";
+ ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>;
+ bus-range = <0 0xff>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+ <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
+ clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k",
+ "peri_26m", "peri_mem";
+
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+
+ iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>;
+ iommu-map-mask = <0>;
+
+ phys = <&pcieport PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+
+ power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
+
+ resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>;
+ reset-names = "mac";
+
+ status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
nor_flash: spi@1132c000 {
compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
reg = <0 0x1132c000 0 0x1000>;
@@ -1775,6 +1822,21 @@ nor_flash: spi@1132c000 {
status = "disabled";
};
+ pciephy: t-phy@11c20700 {
+ compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
+ ranges = <0 0 0x11c20700 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ pcieport: pcie-phy@0 {
+ reg = <0 0x700>;
+ clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
i2c1: i2c@11e00000 {
compatible = "mediatek,mt8188-i2c";
reg = <0 0x11e00000 0 0x1000>,
--
2.46.1.824.gd892dcdcdd-goog
On 10/2/24 19:41, Fei Shao wrote: > > > External email : Please do not click links or open attachments until you > have verified the sender or the content. > > > Add PCIe node and the associated PHY node. > Individual board device tree should enable the nodes as needed. > > Signed-off-by: Fei Shao <fshao@chromium.org> > --- > > arch/arm64/boot/dts/mediatek/mt8188.dtsi | 62 ++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi > index 10195a4e4e9d..9431f3c5c228 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi > @@ -1763,6 +1763,53 @@ xhci0: usb@112b0000 { > status = "disabled"; > }; > > + pcie: pcie@112f0000 { > + compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; > + reg = <0 0x112f0000 0 0x2000>; > + reg-names = "pcie-mac"; It seems the property 'linux,pci-domain = <0>;' is missing? [snip] > + }; > + }; > + > nor_flash: spi@1132c000 { > compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; > reg = <0 0x1132c000 0 0x1000>; > @@ -1775,6 +1822,21 @@ nor_flash: spi@1132c000 { > status = "disabled"; > }; > > + pciephy: t-phy@11c20700 { > + compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; > + ranges = <0 0 0x11c20700 0x700>; > + #address-cells = <1>; > + #size-cells = <1>; > + status = "disabled"; > + The power-domains property is missing. It should be 'power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;' > + pcieport: pcie-phy@0 { > + reg = <0 0x700>; > + clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; > + clock-names = "ref"; > + #phy-cells = <1>; > + }; > + }; > + > i2c1: i2c@11e00000 { > compatible = "mediatek,mt8188-i2c"; > reg = <0 0x11e00000 0 0x1000>, Thanks! Best regards, Macpaul Lin
On Wed, Oct 2, 2024 at 8:42 PM Macpaul Lin <macpaul.lin@mediatek.com> wrote: > > > > On 10/2/24 19:41, Fei Shao wrote: > > > > > > External email : Please do not click links or open attachments until you > > have verified the sender or the content. > > > > > > Add PCIe node and the associated PHY node. > > Individual board device tree should enable the nodes as needed. > > > > Signed-off-by: Fei Shao <fshao@chromium.org> > > --- > > > > arch/arm64/boot/dts/mediatek/mt8188.dtsi | 62 ++++++++++++++++++++++++ > > 1 file changed, 62 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi > > index 10195a4e4e9d..9431f3c5c228 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi > > @@ -1763,6 +1763,53 @@ xhci0: usb@112b0000 { > > status = "disabled"; > > }; > > > > + pcie: pcie@112f0000 { > > + compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; > > + reg = <0 0x112f0000 0 0x2000>; > > + reg-names = "pcie-mac"; > > It seems the property 'linux,pci-domain = <0>;' is missing? I'll add that. I guess the fallback will assign a dynamic ID to it (likely also 0), but explicitly having a static domain ID is never a bad thing. > > [snip] > > > + }; > > + }; > > + > > nor_flash: spi@1132c000 { > > compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; > > reg = <0 0x1132c000 0 0x1000>; > > @@ -1775,6 +1822,21 @@ nor_flash: spi@1132c000 { > > status = "disabled"; > > }; > > > > + pciephy: t-phy@11c20700 { > > + compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; > > + ranges = <0 0 0x11c20700 0x700>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + status = "disabled"; > > + > > The power-domains property is missing. > It should be 'power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;' I dropped this as the binding check was against it, and I thought it was a mistake because other tphy nodes don't seem to have a power domain either. And now I noticed your tphy binding patch in [1] so that explains, except that I still can't tell whether there should be a power domain for a given tphy node... Anyway, I'll fix this one. Thanks! [1]: https://lore.kernel.org/all/20240926101804.22471-1-macpaul.lin@mediatek.com/ Regards, Fei > > > + pcieport: pcie-phy@0 { > > + reg = <0 0x700>; > > + clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; > > + clock-names = "ref"; > > + #phy-cells = <1>; > > + }; > > + }; > > + > > i2c1: i2c@11e00000 { > > compatible = "mediatek,mt8188-i2c"; > > reg = <0 0x11e00000 0 0x1000>, > > Thanks! > Best regards, > Macpaul Lin
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